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vhdl经典源代码——vga控制

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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/temp/95144/vhdl/vga/VGA.vhd" in Library work.
Entity <vga> compiled.
Entity <vga> (Architecture <behv>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <vga> (Architecture <behv>).
WARNING:Xst:819 - "E:/temp/95144/vhdl/vga/VGA.vhd" line 48: The following signals are missing in the process sensitivity list:
   grbx, grby.
Entity <vga> analyzed. Unit <vga> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <vga>.
    Related source file is "E:/temp/95144/vhdl/vga/VGA.vhd".
    Found 10-bit comparator greater for signal <$n0018> created at line 99.
    Found 3-bit xor2 for signal <$n0019> created at line 55.
    Found 6-bit comparator greater for signal <$n0020> created at line 94.
    Found 6-bit comparator less for signal <$n0024> created at line 107.
    Found 6-bit comparator less for signal <$n0025> created at line 107.
    Found 6-bit comparator less for signal <$n0026> created at line 108.
    Found 6-bit comparator less for signal <$n0027> created at line 109.
    Found 6-bit comparator less for signal <$n0028> created at line 110.
    Found 6-bit comparator less for signal <$n0029> created at line 111.
    Found 6-bit comparator less for signal <$n0030> created at line 112.
    Found 10-bit comparator less for signal <$n0031> created at line 116.
    Found 10-bit comparator less for signal <$n0032> created at line 116.
    Found 10-bit comparator less for signal <$n0033> created at line 117.
    Found 10-bit comparator less for signal <$n0034> created at line 118.
    Found 10-bit comparator less for signal <$n0035> created at line 119.
    Found 10-bit comparator less for signal <$n0036> created at line 120.
    Found 10-bit comparator less for signal <$n0037> created at line 121.
    Found 1-bit xor2 for signal <$n0038> created at line 37.
    Found 1-bit xor2 for signal <$n0039> created at line 35.
    Found 1-bit xor2 for signal <$n0040> created at line 36.
    Found 5-bit up counter for signal <cc>.
    Found 2-bit up counter for signal <clk_int>.
    Found 4-bit up counter for signal <fs>.
    Found 9-bit up counter for signal <ll>.
    Found 2-bit up counter for signal <mmd>.
    Summary:
	inferred   5 Counter(s).
	inferred  16 Comparator(s).
	inferred   3 Xor(s).
Unit <vga> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 5
 2-bit up counter                  : 2
 4-bit up counter                  : 1
 5-bit up counter                  : 1
 9-bit up counter                  : 1
# Comparators                      : 16
 10-bit comparator greater         : 1
 10-bit comparator less            : 7
 6-bit comparator greater          : 1
 6-bit comparator less             : 7
# Xors                             : 4
 1-bit xor2                        : 3
 3-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <fs_3> is unconnected in block <vga>.

Optimizing unit <vga> ...




Started process "Translate".

Extracting independent architecture files...
Release 7.1.04i - ngdbuild H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd _ngo -uc vga.ucf -p xc9500xl vga.ngc vga.ngd 

Reading NGO file 'E:/temp/95144/vhdl/vga/vga.ngc' ...

Applying constraints in "vga.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "vga.ngd" ...

Writing NGDBUILD log file "vga.bld"...

NGDBUILD done.




Started process "Fit".

Release 7.1.04i - CPLD Optimizer/Partitioner H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Considering device XC95144XL-10-TQ144.
Flattening design..
Multi-level logic optimization...
Timing optimization..................................
Timing driven global resource optimization
General global resource optimization........
Re-checking device resources ...
Mapping a total of 37 equations into 8 function blocks.WARNING:Cpld:896 - Unable to map all desired signals into function block, FB4,
   because too many function block product terms are required. Buffering output
   signal b to allow all signals assigned to this function block to be placed.
.................

Design vga has been optimized and fit into device XC95144XL-10-TQ144.




Started process "Generate Programming File".

Release 7.1.04i - Programming File Generator H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.




Started process "Generate Timing".

Release 7.1.04i - Timing Report Generator H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for
analysis.
Path tracing ......
The number of paths traced: 252.

.
The number of paths traced: 505.

Checking for asynchronous logic...
No asynchronous logic found.
Generating TA GUI report ...
Generating detailed paths report ...

e:\temp\95144\vhdl\vga/vga_html/tim/timing_report.htm has been created.




Started process "Generate HTML report".

Release 7.1.04i - CPLD HTML Report Processor H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.






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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/VGA is now defined in a different file: was E:/temp/95144/vhdl/vga/VGA.vhd, now is E:/Cindy/working/UE_EXTBOARD/SP3/VHDL/vga/VGA.vhd
WARNING:HDLParsers:3215 - Unit work/VGA/BEHV is now defined in a different file: was E:/temp/95144/vhdl/vga/VGA.vhd, now is E:/Cindy/working/UE_EXTBOARD/SP3/VHDL/vga/VGA.vhd
Compiling vhdl file "E:/Cindy/working/UE_EXTBOARD/SP3/VHDL/vga/VGA.vhd" in Library work.
Entity <vga> compiled.
Entity <vga> (Architecture <behv>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <vga> (Architecture <behv>).
WARNING:Xst:819 - "E:/Cindy/working/UE_EXTBOARD/SP3/VHDL/vga/VGA.vhd" line 50: The following signals are missing in the process sensitivity list:
   grbx, grby.
Entity <vga> analyzed. Unit <vga> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <vga>.
    Related source file is "E:/Cindy/working/UE_EXTBOARD/SP3/VHDL/vga/VGA.vhd".
    Found 10-bit comparator greater for signal <$n0018> created at line 101.
    Found 3-bit xor2 for signal <$n0019> created at line 57.
    Found 6-bit comparator greater for signal <$n0020> created at line 96.
    Found 6-bit comparator less for signal <$n0021> created at line 109.
    Found 6-bit comparator less for signal <$n0022> created at line 109.
    Found 6-bit comparator less for signal <$n0023> created at line 110.
    Found 6-bit comparator less for signal <$n0024> created at line 111.
    Found 6-bit comparator less for signal <$n0025> created at line 112.
    Found 6-bit comparator less for signal <$n0026> created at line 113.
    Found 6-bit comparator less for signal <$n0027> created at line 114.
    Found 10-bit comparator less for signal <$n0028> created at line 118.
    Found 10-bit comparator less for signal <$n0029> created at line 118.
    Found 10-bit comparator less for signal <$n0030> created at line 119.
    Found 10-bit comparator less for signal <$n0031> created at line 120.
    Found 10-bit comparator less for signal <$n0032> created at line 121.
    Found 10-bit comparator less for signal <$n0033> created at line 122.
    Found 10-bit comparator less for signal <$n0034> created at line 123.
    Found 1-bit xor2 for signal <$n0035> created at line 39.
    Found 1-bit xor2 for signal <$n0036> created at line 37.
    Found 1-bit xor2 for signal <$n0037> created at line 38.
    Found 5-bit up counter for signal <cc>.
    Found 2-bit up counter for signal <clk_int>.
    Found 4-bit up counter for signal <fs>.
    Found 3-bit 4-to-1 multiplexer for signal <grbp>.
    Found 9-bit up counter for signal <ll>.
    Found 2-bit up counter for signal <mmd>.
    Summary:
	inferred   5 Counter(s).
	inferred  16 Comparator(s).
	inferred   3 Multiplexer(s).
Unit <vga> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 5
 2-bit up counter                  : 2
 4-bit up counter                  : 1
 5-bit up counter                  : 1
 9-bit up counter                  : 1
# Comparators                      : 16
 10-bit comparator greater         : 1
 10-bit comparator less            : 7
 6-bit comparator greater          : 1
 6-bit comparator less             : 7
# Multiplexers                     : 1
 3-bit 4-to-1 multiplexer          : 1
# Xors                             : 4
 1-bit xor2                        : 3
 3-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *