vga.syr

vhdl经典源代码——vga控制

 Number of bonded IOBs:                  7  out of    141     4%  
 Number of GCLKs:                        2  out of      8    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
fs_2:Q                             | NONE                   | 5     |
cc_4:Q                             | NONE                   | 9     |
clk                                | BUFGP                  | 2     |
orient                             | BUFGP                  | 2     |
clk_int_1:Q                        | NONE                   | 3     |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 5.247ns (Maximum Frequency: 190.572MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 14.412ns
   Maximum combinational path delay: 8.723ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'fs_2:Q'
  Clock period: 3.099ns (frequency: 322.732MHz)
  Total number of paths / destination ports: 15 / 5
-------------------------------------------------------------------------
Delay:               3.099ns (Levels of Logic = 2)
  Source:            cc_2 (FF)
  Destination:       cc_4 (FF)
  Source Clock:      fs_2:Q rising
  Destination Clock: fs_2:Q rising

  Data Path: cc_2 to cc_4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               8   0.626   1.216  cc_2 (cc_2)
     LUT2_L:I0->LO         1   0.479   0.123  cc_Madd__n0000_Mxor_Result<4>_Result1_SW0 (N236)
     LUT4_L:I3->LO         1   0.479   0.000  cc_Madd__n0000_Mxor_Result<4>_Result1 (cc__n0000<4>)
     FD:D                      0.176          cc_4
    ----------------------------------------
    Total                      3.099ns (1.760ns logic, 1.339ns route)
                                       (56.8% logic, 43.2% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'cc_4:Q'
  Clock period: 5.247ns (frequency: 190.572MHz)
  Total number of paths / destination ports: 126 / 18
-------------------------------------------------------------------------
Delay:               5.247ns (Levels of Logic = 2)
  Source:            ll_4 (FF)
  Destination:       ll_7 (FF)
  Source Clock:      cc_4:Q falling
  Destination Clock: cc_4:Q falling

  Data Path: ll_4 to ll_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR_1:C->Q            7   0.626   1.076  ll_4 (ll_4)
     LUT3:I1->O            1   0.479   0.740  _n0016_SW0_SW0 (N238)
     LUT4:I2->O            9   0.479   0.955  _n0016 (_n0016)
     FDR_1:R                   0.892          ll_0
    ----------------------------------------
    Total                      5.247ns (2.476ns logic, 2.771ns route)
                                       (47.2% logic, 52.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 2.355ns (frequency: 424.547MHz)
  Total number of paths / destination ports: 3 / 2
-------------------------------------------------------------------------
Delay:               2.355ns (Levels of Logic = 1)
  Source:            clk_int_1 (FF)
  Destination:       clk_int_1 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: clk_int_1 to clk_int_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               4   0.626   1.074  clk_int_1 (clk_int_1)
     LUT2:I0->O            1   0.479   0.000  clk_int_Madd__n0000_Mxor_Result<1>_Result1 (clk_int__n0000<1>)
     FD:D                      0.176          clk_int_1
    ----------------------------------------
    Total                      2.355ns (1.281ns logic, 1.074ns route)
                                       (54.4% logic, 45.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'orient'
  Clock period: 3.944ns (frequency: 253.579MHz)
  Total number of paths / destination ports: 7 / 4
-------------------------------------------------------------------------
Delay:               3.944ns (Levels of Logic = 1)
  Source:            mmd_0 (FF)
  Destination:       mmd_1 (FF)
  Source Clock:      orient falling
  Destination Clock: orient falling

  Data Path: mmd_0 to mmd_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR_1:C->Q            7   0.626   1.201  mmd_0 (mmd_0)
     LUT2:I0->O            2   0.479   0.745  _n00171 (CHOICE849)
     FDR_1:R                   0.892          mmd_1
    ----------------------------------------
    Total                      3.944ns (1.997ns logic, 1.947ns route)
                                       (50.6% logic, 49.4% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk_int_1:Q'
  Clock period: 2.347ns (frequency: 426.085MHz)
  Total number of paths / destination ports: 6 / 3
-------------------------------------------------------------------------
Delay:               2.347ns (Levels of Logic = 1)
  Source:            fs_0 (FF)
  Destination:       fs_1 (FF)
  Source Clock:      clk_int_1:Q rising
  Destination Clock: clk_int_1:Q rising

  Data Path: fs_0 to fs_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   0.626   1.066  fs_0 (fs_0)
     LUT3:I0->O            1   0.479   0.000  fs_Madd__n0000_Mxor_Result<2>_Result1 (fs__n0000<2>)
     FD:D                      0.176          fs_2
    ----------------------------------------
    Total                      2.347ns (1.281ns logic, 1.066ns route)
                                       (54.6% logic, 45.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'fs_2:Q'
  Total number of paths / destination ports: 27 / 4
-------------------------------------------------------------------------
Offset:              11.815ns (Levels of Logic = 5)
  Source:            cc_4 (FF)
  Destination:       g (PAD)
  Source Clock:      fs_2:Q rising

  Data Path: cc_4 to g
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              18   0.626   1.499  cc_4 (cc_4)
     LUT3:I0->O            1   0.479   0.704  grbp<3>50_SW1 (N248)
     LUT4:I3->O            1   0.479   0.740  grbp<3>50 (CHOICE860)
     LUT4:I2->O            1   0.479   0.740  _n00491_SW0 (N246)
     LUT4:I2->O            1   0.479   0.681  _n00491 (g_OBUF)
     OBUF:I->O                 4.909          g_OBUF (g)
    ----------------------------------------
    Total                     11.815ns (7.451ns logic, 4.364ns route)
                                       (63.1% logic, 36.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'orient'
  Total number of paths / destination ports: 7 / 3
-------------------------------------------------------------------------
Offset:              10.098ns (Levels of Logic = 4)
  Source:            mmd_0 (FF)
  Destination:       g (PAD)
  Source Clock:      orient falling

  Data Path: mmd_0 to g
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR_1:C->Q            7   0.626   0.965  mmd_0 (mmd_0)
     LUT4:I2->O            1   0.479   0.740  grbp<3>50 (CHOICE860)
     LUT4:I2->O            1   0.479   0.740  _n00491_SW0 (N246)
     LUT4:I2->O            1   0.479   0.681  _n00491 (g_OBUF)
     OBUF:I->O                 4.909          g_OBUF (g)
    ----------------------------------------
    Total                     10.098ns (6.972ns logic, 3.126ns route)
                                       (69.0% logic, 31.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'cc_4:Q'
  Total number of paths / destination ports: 47 / 4
-------------------------------------------------------------------------
Offset:              14.412ns (Levels of Logic = 7)
  Source:            ll_4 (FF)
  Destination:       b (PAD)
  Source Clock:      cc_4:Q falling

  Data Path: ll_4 to b
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR_1:C->Q            7   0.626   1.201  ll_4 (ll_4)
     LUT2:I0->O            1   0.479   0.740  grby<1>81 (CHOICE902)
     LUT4:I2->O            1   0.479   0.851  grby<1>89 (CHOICE903)
     LUT4:I1->O            1   0.479   0.704  grby<1>108 (CHOICE905)
     LUT4:I3->O            1   0.479   0.851  grby<1>137 (grby<1>)
     LUT4:I1->O            1   0.479   0.976  Ker01 (N01)
     LUT3:I0->O            1   0.479   0.681  _n00471 (b_OBUF)
     OBUF:I->O                 4.909          b_OBUF (b)
    ----------------------------------------
    Total                     14.412ns (8.409ns logic, 6.003ns route)
                                       (58.3% logic, 41.7% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Delay:               8.723ns (Levels of Logic = 4)
  Source:            orient (PAD)
  Destination:       g (PAD)

  Data Path: orient to g
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     BUFGP:I->O            5   0.357   1.078  orient_BUFGP (orient_BUFGP)
     LUT4:I0->O            1   0.479   0.740  _n00491_SW0 (N246)
     LUT4:I2->O            1   0.479   0.681  _n00491 (g_OBUF)
     OBUF:I->O                 4.909          g_OBUF (g)
    ----------------------------------------
    Total                      8.723ns (6.224ns logic, 2.499ns route)
                                       (71.4% logic, 28.6% route)

=========================================================================
CPU : 15.88 / 17.64 s | Elapsed : 16.00 / 18.00 s
 
--> 

Total memory usage is 92448 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    5 (   0 filtered)
Number of infos    :    1 (   0 filtered)