vga.syr

vhdl经典源代码——vga控制

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: vga.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "vga.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "vga"
Output Format                      : NGC
Target Device                      : xc3s400-5-pq208

---- Source Options
Top Module Name                    : vga
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : vga.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/VGA is now defined in a different file: was E:/temp/95144/vhdl/vga/VGA.vhd, now is E:/Cindy/working/UE_EXTBOARD/SP3/VHDL/vga/VGA.vhd
WARNING:HDLParsers:3215 - Unit work/VGA/BEHV is now defined in a different file: was E:/temp/95144/vhdl/vga/VGA.vhd, now is E:/Cindy/working/UE_EXTBOARD/SP3/VHDL/vga/VGA.vhd
Compiling vhdl file "E:/Cindy/working/UE_EXTBOARD/SP3/VHDL/vga/VGA.vhd" in Library work.
Entity <vga> compiled.
Entity <vga> (Architecture <behv>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <vga> (Architecture <behv>).
WARNING:Xst:819 - "E:/Cindy/working/UE_EXTBOARD/SP3/VHDL/vga/VGA.vhd" line 50: The following signals are missing in the process sensitivity list:
   grbx, grby.
Entity <vga> analyzed. Unit <vga> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <vga>.
    Related source file is "E:/Cindy/working/UE_EXTBOARD/SP3/VHDL/vga/VGA.vhd".
    Found 10-bit comparator greater for signal <$n0018> created at line 101.
    Found 3-bit xor2 for signal <$n0019> created at line 57.
    Found 6-bit comparator greater for signal <$n0020> created at line 96.
    Found 6-bit comparator less for signal <$n0021> created at line 109.
    Found 6-bit comparator less for signal <$n0022> created at line 109.
    Found 6-bit comparator less for signal <$n0023> created at line 110.
    Found 6-bit comparator less for signal <$n0024> created at line 111.
    Found 6-bit comparator less for signal <$n0025> created at line 112.
    Found 6-bit comparator less for signal <$n0026> created at line 113.
    Found 6-bit comparator less for signal <$n0027> created at line 114.
    Found 10-bit comparator less for signal <$n0028> created at line 118.
    Found 10-bit comparator less for signal <$n0029> created at line 118.
    Found 10-bit comparator less for signal <$n0030> created at line 119.
    Found 10-bit comparator less for signal <$n0031> created at line 120.
    Found 10-bit comparator less for signal <$n0032> created at line 121.
    Found 10-bit comparator less for signal <$n0033> created at line 122.
    Found 10-bit comparator less for signal <$n0034> created at line 123.
    Found 1-bit xor2 for signal <$n0035> created at line 39.
    Found 1-bit xor2 for signal <$n0036> created at line 37.
    Found 1-bit xor2 for signal <$n0037> created at line 38.
    Found 5-bit up counter for signal <cc>.
    Found 2-bit up counter for signal <clk_int>.
    Found 4-bit up counter for signal <fs>.
    Found 3-bit 4-to-1 multiplexer for signal <grbp>.
    Found 9-bit up counter for signal <ll>.
    Found 2-bit up counter for signal <mmd>.
    Summary:
	inferred   5 Counter(s).
	inferred  16 Comparator(s).
	inferred   3 Multiplexer(s).
Unit <vga> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 5
 2-bit up counter                  : 2
 4-bit up counter                  : 1
 5-bit up counter                  : 1
 9-bit up counter                  : 1
# Comparators                      : 16
 10-bit comparator greater         : 1
 10-bit comparator less            : 7
 6-bit comparator greater          : 1
 6-bit comparator less             : 7
# Multiplexers                     : 1
 3-bit 4-to-1 multiplexer          : 1
# Xors                             : 4
 1-bit xor2                        : 3
 3-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <3> is unconnected in block <fs>.
WARNING:Xst:1291 - FF/Latch <fs_3> is unconnected in block <vga>.

Optimizing unit <vga> ...
Loading device for application Rf_Device from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block vga, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : vga.ngr
Top Level Output File Name         : vga
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 7

Macro Statistics :
# Registers                        : 5
#      5-bit register              : 5
# Multiplexers                     : 1
#      3-bit 4-to-1 multiplexer    : 1
# Comparators                      : 16
#      10-bit comparator greater   : 1
#      10-bit comparator less      : 7
#      6-bit comparator greater    : 1
#      6-bit comparator less       : 7

Cell Usage :
# BELS                             : 66
#      GND                         : 1
#      INV                         : 2
#      LUT1                        : 1
#      LUT1_L                      : 7
#      LUT2                        : 7
#      LUT2_L                      : 1
#      LUT3                        : 8
#      LUT4                        : 19
#      LUT4_D                      : 1
#      LUT4_L                      : 1
#      MUXCY                       : 8
#      MUXF5                       : 1
#      VCC                         : 1
#      XORCY                       : 8
# FlipFlops/Latches                : 21
#      FD                          : 7
#      FDR                         : 3
#      FDR_1                       : 11
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 5
#      OBUF                        : 5
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-5 

 Number of Slices:                      26  out of   3584     0%  
 Number of Slice Flip Flops:            21  out of   7168     0%  
 Number of 4 input LUTs:                45  out of   7168     0%