📄 vga.rpt
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b <= b_BUFR;
b_BUFR <= ((EXP13_.EXP)
OR (EXP14_.EXP)
OR (orient AND mmd(1) AND mmd(0) AND NOT $OpTx$FX_DC$535)
OR (orient AND mmd(1) AND $OpTx$$OpTx$INV$521_INV$825 AND
grbx(1)/grbx(1)_D2 AND NOT $OpTx$FX_DC$535)
OR (orient AND NOT mmd(1) AND NOT mmd(0) AND NOT grbx(1)/grbx(1)_D2 AND
NOT $OpTx$FX_DC$535)
OR (NOT orient AND NOT mmd(1) AND mmd(0) AND
$OpTx$$OpTx$INV$521_INV$825 AND NOT $OpTx$FX_DC$535)
OR (NOT orient AND NOT mmd(1) AND NOT mmd(0) AND grbx(1)/grbx(1)_D2 AND
NOT $OpTx$FX_DC$535));
FTCPE_cc0: FTCPE port map (cc(0),'1',fs(2),'0','0');
FTCPE_cc1: FTCPE port map (cc(1),cc(0),fs(2),'0','0');
FTCPE_cc2: FTCPE port map (cc(2),cc_T(2),fs(2),'0','0');
cc_T(2) <= (cc(1) AND cc(0));
FTCPE_cc3: FTCPE port map (cc(3),cc_T(3),fs(2),'0','0');
cc_T(3) <= (cc(2) AND cc(1) AND cc(0));
FTCPE_cc4: FTCPE port map (cc(4),cc_T(4),fs(2),'0','0');
cc_T(4) <= (cc(2) AND cc(1) AND cc(3) AND cc(0));
FTCPE_clk_int0: FTCPE port map (clk_int(0),'1',clk,'0','0');
FTCPE_clk_int1: FTCPE port map (clk_int(1),clk_int(0),clk,'0','0');
FTCPE_fs0: FTCPE port map (fs(0),'1',clk_int(1),'0','0');
FTCPE_fs1: FTCPE port map (fs(1),fs(0),clk_int(1),'0','0');
FTCPE_fs2: FTCPE port map (fs(2),fs_T(2),clk_int(1),'0','0');
fs_T(2) <= (fs(0) AND fs(1));
g <= NOT (((cc(4) AND cc(3))
OR (orient AND NOT $OpTx$grbp(3)/grbp(3)_D2_INV$826)
OR (NOT orient AND $OpTx$grbp(3)/grbp(3)_D2_INV$826)
OR (ll(5) AND ll(6) AND ll(7) AND ll(8))));
grbx(1)/grbx(1)_D2 <= ((EXP11_.EXP)
OR ($OpTx$FX_DC$542.EXP)
OR (NOT cc(4) AND cc(2) AND cc(1) AND NOT cc(3))
OR (NOT cc(4) AND cc(2) AND NOT cc(1) AND cc(3))
OR (NOT cc(4) AND cc(2) AND cc(3) AND NOT cc(0))
OR (NOT cc(4) AND cc(1) AND NOT cc(3) AND NOT cc(0))
OR (NOT cc(4) AND NOT cc(1) AND cc(3) AND NOT cc(0)));
grby(1)13/grby(1)13_D2 <= ((NOT ll(8))
OR (vs_OBUF.EXP)
OR ($OpTx$$OpTx$INV$521_INV$825.EXP)
OR (NOT ll(5) AND NOT ll(6))
OR (NOT ll(6) AND NOT ll(7) AND NOT ll(4) AND NOT ll(3))
OR (NOT ll(6) AND NOT ll(7) AND NOT ll(4) AND NOT ll(2))
OR (NOT ll(6) AND NOT ll(4) AND NOT ll(3) AND NOT ll(2)));
grby(3)/grby(3)_D2 <= ((ll(8))
OR (ll(5) AND ll(6) AND ll(7) AND ll(4)));
hs <= NOT ((cc(4) AND cc(3)));
FTCPE_ll0: FTCPE port map (ll(0),'1',NOT cc(4),'0','0');
FTCPE_ll1: FTCPE port map (ll(1),ll_T(1),NOT cc(4),'0','0');
ll_T(1) <= ((NOT ll(0))
OR (ll(5) AND ll(6) AND ll(7) AND NOT ll(4) AND ll(8) AND NOT ll(3) AND
NOT ll(2) AND NOT ll(1)));
FTCPE_ll2: FTCPE port map (ll(2),ll_T(2),NOT cc(4),'0','0');
ll_T(2) <= (ll(0) AND ll(1));
FTCPE_ll3: FTCPE port map (ll(3),ll_T(3),NOT cc(4),'0','0');
ll_T(3) <= (ll(2) AND ll(0) AND ll(1));
FTCPE_ll4: FTCPE port map (ll(4),ll_T(4),NOT cc(4),'0','0');
ll_T(4) <= (ll(3) AND ll(2) AND ll(0) AND ll(1));
FTCPE_ll5: FTCPE port map (ll(5),ll_T(5),NOT cc(4),'0','0');
ll_T(5) <= ((ll(4) AND ll(3) AND ll(2) AND ll(0) AND ll(1))
OR (ll(5) AND ll(6) AND ll(7) AND NOT ll(4) AND ll(8) AND NOT ll(3) AND
NOT ll(2) AND ll(0) AND NOT ll(1)));
FTCPE_ll6: FTCPE port map (ll(6),ll_T(6),NOT cc(4),'0','0');
ll_T(6) <= ((ll(5) AND ll(4) AND ll(3) AND ll(2) AND ll(0) AND ll(1))
OR (ll(5) AND ll(6) AND ll(7) AND NOT ll(4) AND ll(8) AND NOT ll(3) AND
NOT ll(2) AND ll(0) AND NOT ll(1)));
FTCPE_ll7: FTCPE port map (ll(7),ll_T(7),NOT cc(4),'0','0');
ll_T(7) <= ((ll(5) AND ll(6) AND ll(4) AND ll(3) AND ll(2) AND ll(0) AND
ll(1))
OR (ll(5) AND ll(6) AND ll(7) AND NOT ll(4) AND ll(8) AND NOT ll(3) AND
NOT ll(2) AND ll(0) AND NOT ll(1)));
FTCPE_ll8: FTCPE port map (ll(8),ll_T(8),NOT cc(4),'0','0');
ll_T(8) <= ((ll(5) AND ll(6) AND ll(7) AND ll(4) AND ll(3) AND ll(2) AND
ll(0) AND ll(1))
OR (ll(5) AND ll(6) AND ll(7) AND NOT ll(4) AND ll(8) AND NOT ll(3) AND
NOT ll(2) AND ll(0) AND NOT ll(1)));
FDCPE_mmd0: FDCPE port map (mmd(0),mmd_D(0),NOT orient,'0','0');
mmd_D(0) <= (NOT mmd(1) AND NOT mmd(0));
FDCPE_mmd1: FDCPE port map (mmd(1),mmd_D(1),NOT orient,'0','0');
mmd_D(1) <= (NOT mmd(1) AND mmd(0));
r <= NOT (((EXP17_.EXP)
OR (EXP18_.EXP)
OR (cc(4) AND cc(3))
OR (orient AND NOT mmd(1) AND $OpTx$FX_DC$542)
OR (orient AND NOT mmd(1) AND mmd(0) AND NOT $OpTx$FX_DC$543)
OR (orient AND NOT mmd(1) AND mmd(0) AND
$OpTx$$OpTx$INV$521_INV$825)
OR (NOT orient AND mmd(1) AND mmd(0) AND NOT $OpTx$FX_DC$543)));
vs <= NOT ((ll(5) AND ll(6) AND ll(7) AND ll(8)));
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC95144XL-10-TQ144
Pin Signal Pin Signal
No. Name No. Name
1 VCC 73 VCC
2 KPR 74 KPR
3 KPR 75 KPR
4 KPR 76 KPR
5 KPR 77 KPR
6 KPR 78 KPR
7 KPR 79 KPR
8 VCC 80 KPR
9 KPR 81 KPR
10 KPR 82 KPR
11 KPR 83 KPR
12 KPR 84 VCC
13 KPR 85 KPR
14 KPR 86 KPR
15 KPR 87 KPR
16 KPR 88 KPR
17 KPR 89 GND
18 GND 90 GND
19 KPR 91 KPR
20 KPR 92 KPR
21 KPR 93 KPR
22 KPR 94 KPR
23 KPR 95 KPR
24 KPR 96 KPR
25 KPR 97 KPR
26 KPR 98 KPR
27 KPR 99 GND
28 KPR 100 KPR
29 GND 101 KPR
30 KPR 102 KPR
31 KPR 103 KPR
32 KPR 104 KPR
33 KPR 105 KPR
34 KPR 106 KPR
35 KPR 107 KPR
36 GND 108 GND
37 VCC 109 VCC
38 KPR 110 KPR
39 KPR 111 KPR
40 KPR 112 KPR
41 KPR 113 KPR
42 VCC 114 GND
43 KPR 115 KPR
44 KPR 116 KPR
45 KPR 117 KPR
46 KPR 118 KPR
47 GND 119 KPR
48 KPR 120 KPR
49 KPR 121 KPR
50 KPR 122 TDO
51 KPR 123 GND
52 KPR 124 KPR
53 KPR 125 KPR
54 KPR 126 KPR
55 VCC 127 VCC
56 KPR 128 clk
57 KPR 129 KPR
58 KPR 130 KPR
59 KPR 131 KPR
60 KPR 132 KPR
61 KPR 133 KPR
62 GND 134 KPR
63 TDI 135 r
64 KPR 136 KPR
65 TMS 137 g
66 KPR 138 b
67 TCK 139 hs
68 KPR 140 KPR
69 KPR 141 VCC
70 orient 142 vs
71 KPR 143 KPR
72 GND 144 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95144xl-10-TQ144
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25
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