lcd.twr

vhdl经典源代码——LCD控制

--------------------------------------------------------------------------------
Release 7.1.04i Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise e:\cindy\working\ue_extboard\lcd\LCD.ise
-intstyle ise -e 3 -l 3 -s 4 -xml lcd lcd.ncd -o lcd.twr lcd.pcf


Design file:              lcd.ncd
Physical constraint file: lcd.pcf
Device,speed:             xc3s400,-4 (PRODUCTION 1.37 2005-07-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    7.490|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Tue Feb 07 14:36:30 2006
--------------------------------------------------------------------------------



Peak Memory Usage: 83 MB