lcd.syr

vhdl经典源代码——LCD控制

#      LUT3                        : 11
#      LUT3_D                      : 1
#      LUT3_L                      : 3
#      LUT4                        : 54
#      LUT4_D                      : 3
#      LUT4_L                      : 28
#      MUXCY                       : 32
#      MUXF5                       : 10
#      VCC                         : 1
#      XORCY                       : 33
# FlipFlops/Latches                : 44
#      FDC                         : 16
#      FDC_1                       : 1
#      FDCE                        : 5
#      FDCPE                       : 21
#      FDP                         : 1
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 12
#      IBUF                        : 1
#      OBUF                        : 3
#      OBUFT                       : 8
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                      72  out of   3584     2%  
 Number of Slice Flip Flops:            44  out of   7168     0%  
 Number of 4 input LUTs:               128  out of   7168     1%  
 Number of bonded IOBs:                 13  out of    141     9%  
 Number of GCLKs:                        2  out of      8    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 21    |
clk_int:Q                          | BUFG                   | 20    |
tc_clkcnt(_n0020103:O)             | NONE(*)(clkdiv)        | 1     |
clkdiv:Q                           | NONE                   | 2     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 8.987ns (Maximum Frequency: 111.272MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 23.389ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 8.987ns (frequency: 111.272MHz)
  Total number of paths / destination ports: 4221 / 21
-------------------------------------------------------------------------
Delay:               8.987ns (Levels of Logic = 25)
  Source:            clkcnt_13 (FF)
  Destination:       clkcnt_20 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: clkcnt_13 to clkcnt_20
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            2   0.720   1.216  clkcnt_13 (clkcnt_13)
     LUT4:I0->O            1   0.551   0.827  _n002019 (CHOICE75)
     LUT4:I3->O           17   0.551   1.684  _n002023 (CHOICE76)
     LUT3_D:I0->LO         1   0.551   0.000  _n0020103 (N380)
     MUXCY:S->O            1   0.500   0.000  clkcnt_inst_cy_0 (clkcnt_inst_cy_0)
     MUXCY:CI->O           1   0.064   0.000  clkcnt_inst_cy_1 (clkcnt_inst_cy_1)
     MUXCY:CI->O           1   0.064   0.000  clkcnt_inst_cy_2 (clkcnt_inst_cy_2)
     MUXCY:CI->O           1   0.064   0.000  clkcnt_inst_cy_3 (clkcnt_inst_cy_3)
     MUXCY:CI->O           1   0.064   0.000  clkcnt_inst_cy_4 (clkcnt_inst_cy_4)
     MUXCY:CI->O           1   0.064   0.000  clkcnt_inst_cy_5 (clkcnt_inst_cy_5)
     MUXCY:CI->O           1   0.064   0.000  clkcnt_inst_cy_6 (clkcnt_inst_cy_6)
     MUXCY:CI->O           1   0.064   0.000  clkcnt_inst_cy_7 (clkcnt_inst_cy_7)
     MUXCY:CI->O           1   0.064   0.000  clkcnt_inst_cy_8 (clkcnt_inst_cy_8)
     MUXCY:CI->O           1   0.064   0.000  clkcnt_inst_cy_9 (clkcnt_inst_cy_9)
     MUXCY:CI->O           1   0.064   0.000  clkcnt_inst_cy_10 (clkcnt_inst_cy_10)
     MUXCY:CI->O           1   0.064   0.000  clkcnt_inst_cy_11 (clkcnt_inst_cy_11)
     MUXCY:CI->O           1   0.064   0.000  clkcnt_inst_cy_12 (clkcnt_inst_cy_12)
     MUXCY:CI->O           1   0.064   0.000  clkcnt_inst_cy_13 (clkcnt_inst_cy_13)
     MUXCY:CI->O           1   0.064   0.000  clkcnt_inst_cy_14 (clkcnt_inst_cy_14)
     MUXCY:CI->O           1   0.064   0.000  clkcnt_inst_cy_15 (clkcnt_inst_cy_15)
     MUXCY:CI->O           1   0.064   0.000  clkcnt_inst_cy_16 (clkcnt_inst_cy_16)
     MUXCY:CI->O           1   0.064   0.000  clkcnt_inst_cy_17 (clkcnt_inst_cy_17)
     MUXCY:CI->O           1   0.064   0.000  clkcnt_inst_cy_18 (clkcnt_inst_cy_18)
     MUXCY:CI->O           1   0.064   0.000  clkcnt_inst_cy_19 (clkcnt_inst_cy_19)
     MUXCY:CI->O           0   0.064   0.000  clkcnt_inst_cy_20 (clkcnt_inst_cy_20)
     XORCY:CI->O           1   0.904   0.000  clkcnt_inst_sum_20 (clkcnt_inst_sum_20)
     FDCPE:D                   0.203          clkcnt_20
    ----------------------------------------
    Total                      8.987ns (5.260ns logic, 3.727ns route)
                                       (58.5% logic, 41.5% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk_int:Q'
  Clock period: 7.417ns (frequency: 134.825MHz)
  Total number of paths / destination ports: 326 / 24
-------------------------------------------------------------------------
Delay:               7.417ns (Levels of Logic = 8)
  Source:            counter_1 (FF)
  Destination:       counter_5 (FF)
  Source Clock:      clk_int:Q rising
  Destination Clock: clk_int:Q rising

  Data Path: counter_1 to counter_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              8   0.720   1.422  counter_1 (counter_1)
     LUT1_L:I0->LO         1   0.551   0.000  counter_1_rt (counter_1_rt)
     MUXCY:S->O            1   0.500   0.000  lcd__n0031<1>cy (lcd__n0031<1>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd__n0031<2>cy (lcd__n0031<2>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd__n0031<3>cy (lcd__n0031<3>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd__n0031<4>cy (lcd__n0031<4>_cyo)
     XORCY:CI->O           1   0.904   0.996  lcd__n0031<5>_xor (_n0031<5>)
     LUT3:I1->O            1   0.551   0.827  _n0022<5>2 (CHOICE55)
     LUT4_L:I3->LO         1   0.551   0.000  _n0022<5>36 (_n0022<5>)
     FDC:D                     0.203          counter_5
    ----------------------------------------
    Total                      7.417ns (4.172ns logic, 3.245ns route)
                                       (56.2% logic, 43.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock '_n0020103:O'
  Clock period: 3.182ns (frequency: 314.268MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               3.182ns (Levels of Logic = 1)
  Source:            clkdiv (FF)
  Destination:       clkdiv (FF)
  Source Clock:      _n0020103:O rising
  Destination Clock: _n0020103:O rising

  Data Path: clkdiv to clkdiv
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.720   0.907  clkdiv (clkdiv)
     INV:I->O              1   0.551   0.801  _n00561_INV_0 (_n0056)
     FDC:D                     0.203          clkdiv
    ----------------------------------------
    Total                      3.182ns (1.474ns logic, 1.708ns route)
                                       (46.3% logic, 53.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clkdiv:Q'
  Clock period: 4.992ns (frequency: 200.321MHz)
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Delay:               4.992ns (Levels of Logic = 2)
  Source:            clk_int (FF)
  Destination:       clk_int (FF)
  Source Clock:      clkdiv:Q rising
  Destination Clock: clkdiv:Q rising

  Data Path: clk_int to clk_int
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   0.720   0.801  clk_int (clk_int1)
     BUFG:I->O            21   0.401   1.515  clk_int_BUFG (clk_int)
     INV:I->O              1   0.551   0.801  _n00571_INV_0 (_n0057)
     FDC:D                     0.203          clk_int
    ----------------------------------------
    Total                      4.992ns (1.875ns logic, 3.117ns route)
                                       (37.6% logic, 62.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clkdiv:Q'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              7.241ns (Levels of Logic = 1)
  Source:            lcd_e (FF)
  Destination:       lcd_e (PAD)
  Source Clock:      clkdiv:Q falling

  Data Path: lcd_e to lcd_e
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   0.720   0.877  lcd_e (lcd_e_OBUF)
     OBUF:I->O                 5.644          lcd_e_OBUF (lcd_e)
    ----------------------------------------
    Total                      7.241ns (6.364ns logic, 0.877ns route)
                                       (87.9% logic, 12.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_int:Q'
  Total number of paths / destination ports: 3386 / 10
-------------------------------------------------------------------------
Offset:              23.389ns (Levels of Logic = 13)
  Source:            counter_3 (FF)
  Destination:       data<5> (PAD)
  Source Clock:      clk_int:Q rising

  Data Path: counter_3 to data<5>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             14   0.720   1.526  counter_3 (counter_3)
     LUT4:I0->O            1   0.551   0.827  _n003854_SW0 (N353)
     LUT4:I3->O            5   0.551   0.989  _n003854 (CHOICE27)
     LUT3:I2->O            1   0.551   0.000  lcd__n0028<3>lut (N8)
     MUXCY:S->O            1   0.500   0.000  lcd__n0028<3>cy (lcd__n0028<3>_cyo)
     XORCY:CI->O           2   0.904   0.945  lcd__n0028<4>_xor (_n0028<4>)
     LUT4:I2->O            1   0.551   0.869  char_addr<4>_SW1 (N351)
     LUT4:I2->O           13   0.551   1.238  char_addr<4> (char_addr<4>)
     LUT4:I2->O            1   0.551   0.000  aa/Mrom__n0000_inst_mux_f5_5111_F (N367)
     MUXF5:I0->O           1   0.360   1.140  aa/Mrom__n0000_inst_mux_f5_5111 (aa/_n0000<5>)
     LUT2:I0->O            1   0.551   1.140  aa/data<5>1 (data_in<5>)
     LUT4:I0->O            1   0.551   0.827  _n0033<5>1 (N24)
     LUT4:I3->O            1   0.551   0.801  _n0033<5>2 (data_5_OBUFT)
     OBUFT:I->O                5.644          data_5_OBUFT (data<5>)
    ----------------------------------------
    Total                     23.389ns (13.087ns logic, 10.302ns route)
                                       (56.0% logic, 44.0% route)

=========================================================================
CPU : 15.51 / 17.95 s | Elapsed : 15.00 / 17.00 s
 
--> 

Total memory usage is 93472 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    3 (   0 filtered)
Number of infos    :    3 (   0 filtered)