__projnav.log

vhdl经典实例——信号灯控制

Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/Cindy/working/UE_EXTBOARD/buzzer/buzzer.vhd" in Library work.
Entity <buzzer> compiled.
Entity <buzzer> (Architecture <arch>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <buzzer> (Architecture <arch>).
Entity <buzzer> analyzed. Unit <buzzer> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <buzzer>.
    Related source file is "E:/Cindy/working/UE_EXTBOARD/buzzer/buzzer.vhd".
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 16                                             |
    | Inputs             | 1                                              |
    | Outputs            | 8                                              |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $n0003 (positive)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 13-bit adder for signal <$n0016> created at line 60.
    Found 4-bit adder for signal <$n0017> created at line 43.
    Found 4-bit register for signal <clk_div1>.
    Found 13-bit register for signal <clk_div2>.
    Found 22-bit up counter for signal <cnt>.
    Found 1-bit register for signal <out_bit_tmp>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  18 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
Unit <buzzer> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <state[1:3]> with gray encoding.
-------------------
 State | Encoding
-------------------
 000   | 000
 001   | 001
 010   | 011
 011   | 010
 100   | 110
 101   | 111
 110   | 101
 111   | 100
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Adders/Subtractors               : 2
 13-bit adder                      : 1
 4-bit adder                       : 1
# Counters                         : 1
 22-bit up counter                 : 1
# Registers                        : 6
 1-bit register                    : 4
 13-bit register                   : 1
 4-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <buzzer> ...
Loading device for application Rf_Device from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block buzzer, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                      62  out of   3584     1%  
 Number of Slice Flip Flops:            43  out of   7168     0%  
 Number of 4 input LUTs:               112  out of   7168     1%  
 Number of bonded IOBs:                  3  out of    141     2%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 43    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 9.671ns (Maximum Frequency: 103.402MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 7.241ns
   Maximum combinational path delay: No path found

=========================================================================


Project Navigator Auto-Make Log File
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Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
e:\cindy\working\ue_extboard\buzzer/_ngo -nt timestamp -uc buzzer.ucf -p
xc3s400-pq208-4 buzzer.ngc buzzer.ngd 

Reading NGO file 'E:/Cindy/working/UE_EXTBOARD/buzzer/buzzer.ngc' ...

Process interrupted by the user.
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/Cindy/working/UE_EXTBOARD/buzzer/buzzer.vhd" in Library work.
Architecture arch of Entity buzzer is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <buzzer> (Architecture <arch>).
Entity <buzzer> analyzed. Unit <buzzer> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <buzzer>.
    Related source file is "E:/Cindy/working/UE_EXTBOARD/buzzer/buzzer.vhd".
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 16                                             |
    | Inputs             | 1                                              |
    | Outputs            | 8                                              |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $n0003 (positive)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 13-bit adder for signal <$n0016> created at line 60.
    Found 4-bit adder for signal <$n0017> created at line 43.
    Found 4-bit register for signal <clk_div1>.
    Found 13-bit register for signal <clk_div2>.
    Found 22-bit up counter for signal <cnt>.
    Found 1-bit register for signal <out_bit_tmp>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  18 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
Unit <buzzer> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <state[1:3]> with gray encoding.
-------------------
 State | Encoding
-------------------
 000   | 000
 001   | 001
 010   | 011
 011   | 010
 100   | 110
 101   | 111
 110   | 101
 111   | 100
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Adders/Subtractors               : 2
 13-bit adder                      : 1
 4-bit adder                       : 1
# Counters                         : 1
 22-bit up counter                 : 1
# Registers                        : 6
 1-bit register                    : 4
 13-bit register                   : 1
 4-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <buzzer> ...
Loading device for application Rf_Device from file '3s400.nph' in environment D:/Xilinx.