buzzer.twr

vhdl经典实例——信号灯控制

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Release 7.1.04i Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise e:\cindy\working\ue_extboard\buzzer\buzzer.ise
-intstyle ise -e 3 -l 3 -s 4 -xml buzzer buzzer.ncd -o buzzer.twr buzzer.pcf


Design file:              buzzer.ncd
Physical constraint file: buzzer.pcf
Device,speed:             xc3s400,-4 (PRODUCTION 1.37 2005-07-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
out_bit     |    9.633(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    9.216|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Tue Feb 07 13:09:36 2006
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Peak Memory Usage: 83 MB