📄 tb_mc8051_alu_sim.vhd
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-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Test the AND_ACC_RAM command for data widths from 1 up to MAX_DWIDTH --
-----------------------------------------------------------------------------
gen_and_acc_ram: for i in 1 to MAX_DWIDTH generate
-- Values which do not change during AND_ACC_RAM test
rom_data_AND_ACC_RAM(i) <= conv_std_logic_vector(0,MAX_DWIDTH);
hlp_AND_ACC_RAM(i) <= conv_std_logic_vector(0,MAX_DWIDTH);
cmd_AND_ACC_RAM(i) <= conv_std_logic_vector(37,6);
-- Instantiate the ALU unit with the data width set to i
i_mc8051_alu_AND_ACC_RAM : mc8051_alu
generic map (
DWIDTH => i)
port map (
rom_data_i => rom_data_AND_ACC_RAM(i)(i-1 downto 0),
ram_data_i => ram_data_AND_ACC_RAM(i)(i-1 downto 0),
acc_i => acc_AND_ACC_RAM(i)(i-1 downto 0),
-- hlp_i => hlp_AND_ACC_RAM(i)(i-1 downto 0),
cmd_i => cmd_AND_ACC_RAM(i),
cy_i => cy_AND_ACC_RAM(i)((i-1)/4 downto 0),
ov_i => ov_AND_ACC_RAM(i),
new_cy_o => new_cy_AND_ACC_RAM(i)((i-1)/4 downto 0),
new_ov_o => new_ov_AND_ACC_RAM(i),
result_a_o => result_a_AND_ACC_RAM(i)(i-1 downto 0),
result_b_o => result_b_AND_ACC_RAM(i)(i-1 downto 0));
-- Call the test procedure for the AND_ACC_RAM command
PROC_AND (DWIDTH => i,
PROP_DELAY => PROP_DELAY,
s_cyi => new_cy_AND_ACC_RAM(i)((i-1)/4 downto 0),
s_ovi => new_ov_AND_ACC_RAM(i),
s_result => result_a_AND_ACC_RAM(i)(i-1 downto 0),
s_cyo => cy_AND_ACC_RAM(i)((i-1)/4 downto 0),
s_ovo => ov_AND_ACC_RAM(i),
s_operanda => acc_AND_ACC_RAM(i)(i-1 downto 0),
s_operandb => ram_data_AND_ACC_RAM(i)(i-1 downto 0),
s_and_end => end_AND_ACC_RAM(i));
end generate gen_and_acc_ram;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Test the OR_ACC_RAM command for data widths from 1 up to MAX_DWIDTH --
-----------------------------------------------------------------------------
gen_or_acc_ram: for i in 1 to MAX_DWIDTH generate
-- Values which do not change during OR_ACC_RAM test
rom_data_OR_ACC_RAM(i) <= conv_std_logic_vector(0,MAX_DWIDTH);
hlp_OR_ACC_RAM(i) <= conv_std_logic_vector(0,MAX_DWIDTH);
cmd_OR_ACC_RAM(i) <= conv_std_logic_vector(44,6);
-- Instantiate the ALU unit with the data width set to i
i_mc8051_alu_OR_ACC_RAM : mc8051_alu
generic map (
DWIDTH => i)
port map (
rom_data_i => rom_data_OR_ACC_RAM(i)(i-1 downto 0),
ram_data_i => ram_data_OR_ACC_RAM(i)(i-1 downto 0),
acc_i => acc_OR_ACC_RAM(i)(i-1 downto 0),
-- hlp_i => hlp_OR_ACC_RAM(i)(i-1 downto 0),
cmd_i => cmd_OR_ACC_RAM(i),
cy_i => cy_OR_ACC_RAM(i)((i-1)/4 downto 0),
ov_i => ov_OR_ACC_RAM(i),
new_cy_o => new_cy_OR_ACC_RAM(i)((i-1)/4 downto 0),
new_ov_o => new_ov_OR_ACC_RAM(i),
result_a_o => result_a_OR_ACC_RAM(i)(i-1 downto 0),
result_b_o => result_b_OR_ACC_RAM(i)(i-1 downto 0));
-- Call the test procedure for the OR_ACC_RAM command
PROC_OR (DWIDTH => i,
PROP_DELAY => PROP_DELAY,
s_cyi => new_cy_OR_ACC_RAM(i)((i-1)/4 downto 0),
s_ovi => new_ov_OR_ACC_RAM(i),
s_result => result_a_OR_ACC_RAM(i)(i-1 downto 0),
s_cyo => cy_OR_ACC_RAM(i)((i-1)/4 downto 0),
s_ovo => ov_OR_ACC_RAM(i),
s_operanda => acc_OR_ACC_RAM(i)(i-1 downto 0),
s_operandb => ram_data_OR_ACC_RAM(i)(i-1 downto 0),
s_or_end => end_OR_ACC_RAM(i));
end generate gen_or_acc_ram;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Test the XOR_ACC_RAM command for data widths from 1 up to MAX_DWIDTH --
-----------------------------------------------------------------------------
gen_xor_acc_ram: for i in 1 to MAX_DWIDTH generate
-- Values which do not change during XOR_ACC_RAM test
rom_data_XOR_ACC_RAM(i) <= conv_std_logic_vector(0,MAX_DWIDTH);
hlp_XOR_ACC_RAM(i) <= conv_std_logic_vector(0,MAX_DWIDTH);
cmd_XOR_ACC_RAM(i) <= conv_std_logic_vector(47,6);
-- Instantiate the ALU unit with the data width set to i
i_mc8051_alu_XOR_ACC_RAM : mc8051_alu
generic map (
DWIDTH => i)
port map (
rom_data_i => rom_data_XOR_ACC_RAM(i)(i-1 downto 0),
ram_data_i => ram_data_XOR_ACC_RAM(i)(i-1 downto 0),
acc_i => acc_XOR_ACC_RAM(i)(i-1 downto 0),
-- hlp_i => hlp_XOR_ACC_RAM(i)(i-1 downto 0),
cmd_i => cmd_XOR_ACC_RAM(i),
cy_i => cy_XOR_ACC_RAM(i)((i-1)/4 downto 0),
ov_i => ov_XOR_ACC_RAM(i),
new_cy_o => new_cy_XOR_ACC_RAM(i)((i-1)/4 downto 0),
new_ov_o => new_ov_XOR_ACC_RAM(i),
result_a_o => result_a_XOR_ACC_RAM(i)(i-1 downto 0),
result_b_o => result_b_XOR_ACC_RAM(i)(i-1 downto 0));
-- Call the test procedure for the XOR_ACC_RAM command
PROC_XOR (DWIDTH => i,
PROP_DELAY => PROP_DELAY,
s_cyi => new_cy_XOR_ACC_RAM(i)((i-1)/4 downto 0),
s_ovi => new_ov_XOR_ACC_RAM(i),
s_result => result_a_XOR_ACC_RAM(i)(i-1 downto 0),
s_cyo => cy_XOR_ACC_RAM(i)((i-1)/4 downto 0),
s_ovo => ov_XOR_ACC_RAM(i),
s_operanda => acc_XOR_ACC_RAM(i)(i-1 downto 0),
s_operandb => ram_data_XOR_ACC_RAM(i)(i-1 downto 0),
s_xor_end => end_XOR_ACC_RAM(i));
end generate gen_xor_acc_ram;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Test the ADD_ACC_RAM command for data widths from 1 up to MAX_DWIDTH --
-----------------------------------------------------------------------------
gen_add_acc_ram: for i in 1 to MAX_DWIDTH generate
-- Values which do not change during ADD_ACC_RAM test
rom_data_ADD_ACC_RAM(i) <= conv_std_logic_vector(0, MAX_DWIDTH);
hlp_ADD_ACC_RAM(i) <= conv_std_logic_vector(0, MAX_DWIDTH);
cmd_ADD_ACC_RAM(i) <= conv_std_logic_vector(33, 6);
-- Instantiate the ALU unit with the data width set to i
i_mc8051_alu_ADD_ACC_RAM : mc8051_alu
generic map (
DWIDTH => i)
port map (
rom_data_i => rom_data_ADD_ACC_RAM(i)(i-1 downto 0),
ram_data_i => ram_data_ADD_ACC_RAM(i)(i-1 downto 0),
acc_i => acc_ADD_ACC_RAM(i)(i-1 downto 0),
-- hlp_i => hlp_ADD_ACC_RAM(i)(i-1 downto 0),
cmd_i => cmd_ADD_ACC_RAM(i),
cy_i => cy_ADD_ACC_RAM(i)((i-1)/4 downto 0),
ov_i => ov_ADD_ACC_RAM(i),
new_cy_o => new_cy_ADD_ACC_RAM(i)((i-1)/4 downto 0),
new_ov_o => new_ov_ADD_ACC_RAM(i),
result_a_o => result_a_ADD_ACC_RAM(i)(i-1 downto 0),
result_b_o => result_b_ADD_ACC_RAM(i)(i-1 downto 0));
-- Call the test procedure for the ADD_ACC_RAM command
PROC_ADD (DWIDTH => i,
PROP_DELAY => PROP_DELAY,
ADD_CARRY => false,
s_cyi => new_cy_ADD_ACC_RAM(i)((i-1)/4 downto 0),
s_ovi => new_ov_ADD_ACC_RAM(i),
s_result => result_a_ADD_ACC_RAM(i)(i-1 downto 0),
s_cyo => cy_ADD_ACC_RAM(i)((i-1)/4 downto 0),
s_ovo => ov_ADD_ACC_RAM(i),
s_operanda => acc_ADD_ACC_RAM(i)(i-1 downto 0),
s_operandb => ram_data_ADD_ACC_RAM(i)(i-1 downto 0),
s_add_end => end_ADD_ACC_RAM(i));
end generate gen_add_acc_ram;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Test the ADDC_ACC_RAM command for data widths from 1 up to MAX_DWIDTH --
-----------------------------------------------------------------------------
gen_addc_acc_ram: for i in 1 to MAX_DWIDTH generate
-- Values which do not change during ADDC_ACC_RAM test
rom_data_ADDC_ACC_RAM(i) <= conv_std_logic_vector(0, MAX_DWIDTH);
hlp_ADDC_ACC_RAM(i) <= conv_std_logic_vector(0, MAX_DWIDTH);
cmd_ADDC_ACC_RAM(i) <= conv_std_logic_vector(35, 6);
-- Instantiate the ALU unit with the data width set to i
i_mc8051_alu_ADDC_ACC_RAM : mc8051_alu
generic map (
DWIDTH => i)
port map (
rom_data_i => rom_data_ADDC_ACC_RAM(i)(i-1 downto 0),
ram_data_i => ram_data_ADDC_ACC_RAM(i)(i-1 downto 0),
acc_i => acc_ADDC_ACC_RAM(i)(i-1 downto 0),
-- hlp_i => hlp_ADDC_ACC_RAM(i)(i-1 downto 0),
cmd_i => cmd_ADDC_ACC_RAM(i),
cy_i => cy_ADDC_ACC_RAM(i)((i-1)/4 downto 0),
ov_i => ov_ADDC_ACC_RAM(i),
new_cy_o => new_cy_ADDC_ACC_RAM(i)((i-1)/4 downto 0),
new_ov_o => new_ov_ADDC_ACC_RAM(i),
result_a_o => result_a_ADDC_ACC_RAM(i)(i-1 downto 0),
result_b_o => result_b_ADDC_ACC_RAM(i)(i-1 downto 0));
-- Call the test procedure for the ADDC_ACC_RAM command
PROC_ADD (DWIDTH => i,
PROP_DELAY => PROP_DELAY,
ADD_CARRY => true,
s_cyi => new_cy_ADDC_ACC_RAM(i)((i-1)/4 downto 0),
s_ovi => new_ov_ADDC_ACC_RAM(i),
s_result => result_a_ADDC_ACC_RAM(i)(i-1 downto 0),
s_cyo => cy_ADDC_ACC_RAM(i)((i-1)/4 downto 0),
s_ovo => ov_ADDC_ACC_RAM(i),
s_operanda => acc_ADDC_ACC_RAM(i)(i-1 downto 0),
s_operandb => ram_data_ADDC_ACC_RAM(i)(i-1 downto 0),
s_add_end => end_ADDC_ACC_RAM(i));
end generate gen_addc_acc_ram;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Test the SUB_ACC_RAM command for data widths from 1 up to MAX_DWIDTH --
-----------------------------------------------------------------------------
gen_sub_acc_ram: for i in 1 to MAX_DWIDTH generate
-- Values which do not change during SUB_ACC_RAM test
rom_data_SUB_ACC_RAM(i) <= conv_std_logic_vector(0, MAX_DWIDTH);
hlp_SUB_ACC_RAM(i) <= conv_std_logic_vector(0, MAX_DWIDTH);
cmd_SUB_ACC_RAM(i) <= conv_std_logic_vector(40, 6);
-- Instantiate the ALU unit with the data width set to i
i_mc8051_alu_SUB_ACC_RAM : mc8051_alu
generic map (
DWIDTH => i)
port map (
rom_data_i => rom_data_SUB_ACC_RAM(i)(i-1 downto 0),
ram_data_i => ram_data_SUB_ACC_RAM(i)(i-1 downto 0),
acc_i => acc_SUB_ACC_RAM(i)(i-1 downto 0),
-- hlp_i => hlp_SUB_ACC_RAM(i)(i-1 downto 0),
cmd_i => cmd_SUB_ACC_RAM(i),
cy_i => cy_SUB_ACC_RAM(i)((i-1)/4 downto 0),
ov_i => ov_SUB_ACC_RAM(i),
new_cy_o => new_cy_SUB_ACC_RAM(i)((i-1)/4 downto 0),
new_ov_o => new_ov_SUB_ACC_RAM(i),
result_a_o => result_a_SUB_ACC_RAM(i)(i-1 downto 0),
result_b_o => result_b_SUB_ACC_RAM(i)(i-1 downto 0));
-- Call the test procedure for the SUB_ACC_RAM command
PROC_SUB (DWIDTH => i,
PROP_DELAY => PROP_DELAY,
s_cyi => new_cy_SUB_ACC_RAM(i)((i-1)/4 downto 0),
s_ovi => new_ov_SUB_ACC_RAM(i),
s_result => result_a_SUB_ACC_RAM(i)(i-1 downto 0),
s_cyo => cy_SUB_ACC_RAM(i)((i-1)/4 downto 0),
s_ovo => ov_SUB_ACC_RAM(i),
s_operanda => acc_SUB_ACC_RAM(i)(i-1 downto 0),
s_operandb => ram_data_SUB_ACC_RAM(i)(i-1 downto 0),
s_sub_end => end_SUB_ACC_RAM(i));
end generate gen_sub_acc_ram;
-----------------------------------------------------------------------------
gen_pass: for i in 1 to MAX_DWIDTH generate
pass(i+1) <= end_DA(i)
and pass(i)
and end_DIV_ACC_RAM(i)
and end_AND_ACC_RAM(i)
and end_OR_ACC_RAM(i)
and end_XOR_ACC_RAM(i)
and end_ADD_ACC_RAM(i)
and end_ADDC_ACC_RAM(i)
and end_SUB_ACC_RAM(i)
and end_MUL_ACC_RAM(i);
end generate gen_pass;
-- The following process guarantees that the simulation is not stopped
-- (despite the ocurrence of an error situation) till all the instantiated
-- designs under test have finished their whole test.
p_endsim: process
begin -- process p_endsim
wait until pass(MAX_DWIDTH+1) = true;
assert false report "SIMULATION ENDED SUCCESSFULLY !!!" severity failure;
end process p_endsim;
end sim;
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