tb_mc8051_alu_sim.vhd

VHDL写的8051内核,可用的,好用,有兴趣可下载,在外国网站下载的

    std_logic_vector(MAX_DWIDTH*2-1 downto 0);
  type t_data_MUL_ACC_RAM is array (1 to MAX_DWIDTH) of
    std_logic_vector(MAX_DWIDTH-1 downto 0);
  type t_cmd_MUL_ACC_RAM is array (1 to MAX_DWIDTH) of
    std_logic_vector(5 downto 0);
  type t_ov_MUL_ACC_RAM is array (1 to MAX_DWIDTH) of std_logic;
  type t_end_MUL_ACC_RAM is array (1 to MAX_DWIDTH) of boolean;
  type t_cy_MUL_ACC_RAM is array (1 to MAX_DWIDTH) of
    std_logic_vector((MAX_DWIDTH-1)/4 downto 0);
  
  type t_data_STIM is array (1 to MAX_DWIDTH) of
    std_logic_vector(MAX_DWIDTH-1 downto 0);
  type t_cmd_STIM is array (1 to MAX_DWIDTH) of std_logic_vector(5 downto 0);
  type t_cy_STIM is array (1 to MAX_DWIDTH) of
    std_logic_vector((MAX_DWIDTH-1)/4 downto 0);
  type t_ov_STIM is array (1 to MAX_DWIDTH) of std_logic;
  type t_end_STIM is array (1 to MAX_DWIDTH) of boolean;

  type t_pass is array (1 to MAX_DWIDTH+1) of boolean;

  signal rom_data_DA : t_data_DA;
  signal ram_data_DA : t_data_DA;
  signal acc_DA : t_data_DA;
  signal hlp_DA : t_data_DA;
  signal cmd_DA : t_cmd_DA;
  signal cy_DA : t_cy_DA;
  signal ov_DA : t_ov_DA;
  signal new_cy_DA : t_cy_DA;
  signal new_ov_DA : t_ov_DA;
  signal result_a_DA : t_data_DA;
  signal result_b_DA : t_data_DA;
  signal end_DA : t_end_DA;

  signal rom_data_DIV_ACC_RAM : t_data_DIV_ACC_RAM;
  signal ram_data_DIV_ACC_RAM : t_data_DIV_ACC_RAM;
  signal acc_DIV_ACC_RAM : t_data_DIV_ACC_RAM;
  signal hlp_DIV_ACC_RAM : t_data_DIV_ACC_RAM;
  signal cmd_DIV_ACC_RAM : t_cmd_DIV_ACC_RAM;
  signal cy_DIV_ACC_RAM : t_cy_DIV_ACC_RAM;
  signal ov_DIV_ACC_RAM : t_ov_DIV_ACC_RAM;
  signal new_cy_DIV_ACC_RAM : t_cy_DIV_ACC_RAM;
  signal new_ov_DIV_ACC_RAM : t_ov_DIV_ACC_RAM;
  signal result_a_DIV_ACC_RAM : t_data_DIV_ACC_RAM;
  signal result_b_DIV_ACC_RAM : t_data_DIV_ACC_RAM;
  signal end_DIV_ACC_RAM : t_end_DIV_ACC_RAM;

  signal rom_data_MUL_ACC_RAM : t_data_MUL_ACC_RAM;
  signal ram_data_MUL_ACC_RAM : t_data_MUL_ACC_RAM;
  signal acc_MUL_ACC_RAM : t_data_MUL_ACC_RAM;
  signal hlp_MUL_ACC_RAM : t_data_MUL_ACC_RAM;
  signal cmd_MUL_ACC_RAM : t_cmd_MUL_ACC_RAM;
  signal cy_MUL_ACC_RAM : t_cy_MUL_ACC_RAM;
  signal ov_MUL_ACC_RAM : t_ov_MUL_ACC_RAM;
  signal new_cy_MUL_ACC_RAM : t_cy_MUL_ACC_RAM;
  signal new_ov_MUL_ACC_RAM : t_ov_MUL_ACC_RAM;
  signal result_a_MUL_ACC_RAM : t_data_MUL_ACC_RAM;
  signal result_b_MUL_ACC_RAM : t_data_MUL_ACC_RAM;
  signal product_MUL_ACC_RAM : t_product_MUL_ACC_RAM;
  signal end_MUL_ACC_RAM : t_end_MUL_ACC_RAM;

  signal rom_data_AND_ACC_RAM : t_data_STIM;
  signal ram_data_AND_ACC_RAM : t_data_STIM;
  signal acc_AND_ACC_RAM : t_data_STIM;
  signal hlp_AND_ACC_RAM : t_data_STIM;
  signal cmd_AND_ACC_RAM : t_cmd_STIM;
  signal cy_AND_ACC_RAM : t_cy_STIM;
  signal ov_AND_ACC_RAM : t_ov_STIM;
  signal new_cy_AND_ACC_RAM : t_cy_STIM;
  signal new_ov_AND_ACC_RAM : t_ov_STIM;
  signal result_a_AND_ACC_RAM : t_data_STIM;
  signal result_b_AND_ACC_RAM : t_data_STIM;
  signal end_AND_ACC_RAM : t_end_STIM;

  signal rom_data_OR_ACC_RAM : t_data_STIM;
  signal ram_data_OR_ACC_RAM : t_data_STIM;
  signal acc_OR_ACC_RAM : t_data_STIM;
  signal hlp_OR_ACC_RAM : t_data_STIM;
  signal cmd_OR_ACC_RAM : t_cmd_STIM;
  signal cy_OR_ACC_RAM : t_cy_STIM;
  signal ov_OR_ACC_RAM : t_ov_STIM;
  signal new_cy_OR_ACC_RAM : t_cy_STIM;
  signal new_ov_OR_ACC_RAM : t_ov_STIM;
  signal result_a_OR_ACC_RAM : t_data_STIM;
  signal result_b_OR_ACC_RAM : t_data_STIM;
  signal end_OR_ACC_RAM : t_end_STIM;

  signal rom_data_XOR_ACC_RAM : t_data_STIM;
  signal ram_data_XOR_ACC_RAM : t_data_STIM;
  signal acc_XOR_ACC_RAM : t_data_STIM;
  signal hlp_XOR_ACC_RAM : t_data_STIM;
  signal cmd_XOR_ACC_RAM : t_cmd_STIM;
  signal cy_XOR_ACC_RAM : t_cy_STIM;
  signal ov_XOR_ACC_RAM : t_ov_STIM;
  signal new_cy_XOR_ACC_RAM : t_cy_STIM;
  signal new_ov_XOR_ACC_RAM : t_ov_STIM;
  signal result_a_XOR_ACC_RAM : t_data_STIM;
  signal result_b_XOR_ACC_RAM : t_data_STIM;
  signal end_XOR_ACC_RAM : t_end_STIM;

  signal rom_data_ADD_ACC_RAM : t_data_STIM;
  signal ram_data_ADD_ACC_RAM : t_data_STIM;
  signal acc_ADD_ACC_RAM : t_data_STIM;
  signal hlp_ADD_ACC_RAM : t_data_STIM;
  signal cmd_ADD_ACC_RAM : t_cmd_STIM;
  signal cy_ADD_ACC_RAM : t_cy_STIM;
  signal ov_ADD_ACC_RAM : t_ov_STIM;
  signal new_cy_ADD_ACC_RAM : t_cy_STIM;
  signal new_ov_ADD_ACC_RAM : t_ov_STIM;
  signal result_a_ADD_ACC_RAM : t_data_STIM;
  signal result_b_ADD_ACC_RAM : t_data_STIM;
  signal end_ADD_ACC_RAM : t_end_STIM;
  
  signal rom_data_ADDC_ACC_RAM : t_data_STIM;
  signal ram_data_ADDC_ACC_RAM : t_data_STIM;
  signal acc_ADDC_ACC_RAM : t_data_STIM;
  signal hlp_ADDC_ACC_RAM : t_data_STIM;
  signal cmd_ADDC_ACC_RAM : t_cmd_STIM;
  signal cy_ADDC_ACC_RAM : t_cy_STIM;
  signal ov_ADDC_ACC_RAM : t_ov_STIM;
  signal new_cy_ADDC_ACC_RAM : t_cy_STIM;
  signal new_ov_ADDC_ACC_RAM : t_ov_STIM;
  signal result_a_ADDC_ACC_RAM : t_data_STIM;
  signal result_b_ADDC_ACC_RAM : t_data_STIM;
  signal end_ADDC_ACC_RAM : t_end_STIM;
  
  signal rom_data_SUB_ACC_RAM : t_data_STIM;
  signal ram_data_SUB_ACC_RAM : t_data_STIM;
  signal acc_SUB_ACC_RAM : t_data_STIM;
  signal hlp_SUB_ACC_RAM : t_data_STIM;
  signal cmd_SUB_ACC_RAM : t_cmd_STIM;
  signal cy_SUB_ACC_RAM : t_cy_STIM;
  signal ov_SUB_ACC_RAM : t_ov_STIM;
  signal new_cy_SUB_ACC_RAM : t_cy_STIM;
  signal new_ov_SUB_ACC_RAM : t_ov_STIM;
  signal result_a_SUB_ACC_RAM : t_data_STIM;
  signal result_b_SUB_ACC_RAM : t_data_STIM;
  signal end_SUB_ACC_RAM : t_end_STIM;

  signal pass : t_pass := (others => true);

begin

  -----------------------------------------------------------------------------
  -- Test the DA command for data widths from 1 up to MAX_DWIDTH             --
  -----------------------------------------------------------------------------
  gen_da: for i in 1 to MAX_DWIDTH generate
    -- Values which do not change during DA test
    rom_data_DA(i) <= conv_std_logic_vector(0,MAX_DWIDTH);
    ram_data_DA(i) <= conv_std_logic_vector(0,MAX_DWIDTH);
    hlp_DA(i)      <= conv_std_logic_vector(0,MAX_DWIDTH);
    cmd_DA(i)      <= conv_std_logic_vector(32,6);
    ov_DA(i)       <= '0';
    -- Instantiate the ALU unit with the data width set to i
    i_mc8051_alu_DA : mc8051_alu    
      generic map (                 
        DWIDTH => i)                
      port map (                    
        rom_data_i => rom_data_DA(i)(i-1 downto 0), 
        ram_data_i => ram_data_DA(i)(i-1 downto 0), 
        acc_i      => acc_DA(i)(i-1 downto 0),      
--        hlp_i      => hlp_DA(i)(i-1 downto 0),      
        cmd_i      => cmd_DA(i),      
        cy_i       => cy_DA(i)((i-1)/4 downto 0),       
        ov_i       => ov_DA(i),       
        new_cy_o   => new_cy_DA(i)((i-1)/4 downto 0),   
        new_ov_o   => new_ov_DA(i),   
        result_a_o => result_a_DA(i)(i-1 downto 0), 
        result_b_o => result_b_DA(i)(i-1 downto 0));
    -- Call the test procedure for the DA command
    PROC_DA (DWIDTH     => i,
             PROP_DELAY => PROP_DELAY,
             s_datao    => acc_DA(i)(i-1 downto 0),
             s_cy       => cy_DA(i)((i-1)/4 downto 0),
             s_datai    => result_a_DA(i)(i-1 downto 0),
             s_cyi      => new_cy_DA(i)((i-1)/4 downto 0),
             s_da_end   => end_DA(i));
  end generate GEN_DA;
  -----------------------------------------------------------------------------
  
  -----------------------------------------------------------------------------
  -- Test the DIV_ACC_RAM command for data widths from 1 up to MAX_DWIDTH    --
  -----------------------------------------------------------------------------
  gen_div_acc_ram: for i in 1 to MAX_DWIDTH generate
    -- Values which do not change during DIV_ACC_RAM test
    rom_data_DIV_ACC_RAM(i) <= conv_std_logic_vector(0,MAX_DWIDTH);
    hlp_DIV_ACC_RAM(i)      <= conv_std_logic_vector(0,MAX_DWIDTH);
    cmd_DIV_ACC_RAM(i)      <= conv_std_logic_vector(43,6);
    -- Instantiate the ALU unit with the data width set to i
    i_mc8051_alu_DIV_ACC_RAM : mc8051_alu    
      generic map (                 
        DWIDTH => i)                
      port map (                    
        rom_data_i => rom_data_DIV_ACC_RAM(i)(i-1 downto 0), 
        ram_data_i => ram_data_DIV_ACC_RAM(i)(i-1 downto 0), 
        acc_i      => acc_DIV_ACC_RAM(i)(i-1 downto 0),      
--        hlp_i      => hlp_DIV_ACC_RAM(i)(i-1 downto 0),      
        cmd_i      => cmd_DIV_ACC_RAM(i),      
        cy_i       => cy_DIV_ACC_RAM(i)((i-1)/4 downto 0),       
        ov_i       => ov_DIV_ACC_RAM(i),       
        new_cy_o   => new_cy_DIV_ACC_RAM(i)((i-1)/4 downto 0),   
        new_ov_o   => new_ov_DIV_ACC_RAM(i),   
        result_a_o => result_a_DIV_ACC_RAM(i)(i-1 downto 0), 
        result_b_o => result_b_DIV_ACC_RAM(i)(i-1 downto 0));
    PROC_DIV_ACC_RAM (DWIDTH => i,
             PROP_DELAY      => PROP_DELAY,
             s_cyi           => new_cy_DIV_ACC_RAM(i)((i-1)/4 downto 0),
             s_ovi           => new_ov_DIV_ACC_RAM(i),
             s_qutnt         => result_a_DIV_ACC_RAM(i)(i-1 downto 0),
             s_rmndr         => result_b_DIV_ACC_RAM(i)(i-1 downto 0),
             s_cyo           => cy_DIV_ACC_RAM(i)((i-1)/4 downto 0),
             s_ovo           => ov_DIV_ACC_RAM(i),
             s_dvdnd         => acc_DIV_ACC_RAM(i)(i-1 downto 0),
             s_dvsor         => ram_data_DIV_ACC_RAM(i)(i-1 downto 0),
             s_dvdr_end      => end_DIV_ACC_RAM(i));
  end generate gen_div_acc_ram;
  -----------------------------------------------------------------------------

  -----------------------------------------------------------------------------
  -- Test the MUL_ACC_RAM command for data widths from 1 up to MAX_DWIDTH  --
  -----------------------------------------------------------------------------
  gen_mul_acc_ram            : for i in 1 to MAX_DWIDTH generate
    -- Values which do not change during MUL_ACC_RAM test
    product_MUL_ACC_RAM(i)(i-1 downto 0)   <=
      result_a_MUL_ACC_RAM(i)(i-1 downto 0);
    product_MUL_ACC_RAM(i)(i*2-1 downto i) <=
      result_b_MUL_ACC_RAM(i)(i-1 downto 0);
    rom_data_MUL_ACC_RAM(i)            <= conv_std_logic_vector(0, MAX_DWIDTH);
    hlp_MUL_ACC_RAM(i)                 <= conv_std_logic_vector(0, MAX_DWIDTH);
    cmd_MUL_ACC_RAM(i)                 <= conv_std_logic_vector(42, 6);
    -- Instantiate the ALU unit with the data width set to i
    i_mc8051_alu_MUL_ACC_RAM : mc8051_alu
      generic map (
        DWIDTH               => i)
      port map (
        rom_data_i           => rom_data_MUL_ACC_RAM(i)(i-1 downto 0),
        ram_data_i           => ram_data_MUL_ACC_RAM(i)(i-1 downto 0),
        acc_i                => acc_MUL_ACC_RAM(i)(i-1 downto 0),
--        hlp_i                => hlp_MUL_ACC_RAM(i)(i-1 downto 0),
        cmd_i                => cmd_MUL_ACC_RAM(i),
        cy_i                 => cy_MUL_ACC_RAM(i)((i-1)/4 downto 0),
        ov_i                 => ov_MUL_ACC_RAM(i),
        new_cy_o             => new_cy_MUL_ACC_RAM(i)((i-1)/4 downto 0),
        new_ov_o             => new_ov_MUL_ACC_RAM(i),
        result_a_o           => result_a_MUL_ACC_RAM(i)(i-1 downto 0),
        result_b_o           => result_b_MUL_ACC_RAM(i)(i-1 downto 0));
    PROC_MUL_ACC_RAM (DWIDTH => i,
             PROP_DELAY      => PROP_DELAY,
             s_cyi           => new_cy_MUL_ACC_RAM(i)((i-1)/4 downto 0),
             s_ovi           => new_ov_MUL_ACC_RAM(i),
             s_product       => product_MUL_ACC_RAM(i)(i*2-1 downto 0),
             s_cyo           => cy_MUL_ACC_RAM(i)((i-1)/4 downto 0),
             s_ovo           => ov_MUL_ACC_RAM(i),
             s_mltplcnd      => acc_MUL_ACC_RAM(i)(i-1 downto 0),
             s_mltplctr      => ram_data_MUL_ACC_RAM(i)(i-1 downto 0),
             s_mul_end       => end_MUL_ACC_RAM(i));
  end generate gen_mul_acc_ram;