📄 tb_mc8051_alu_sim.vhd
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report "ERROR in " & IMAGE(DWIDTH) & "bit logical XOR operation!"
severity failure;
end loop; -- f
end loop; -- i
end loop; -- j
assert false
report "********* " & IMAGE(DWIDTH)
& "BIT XOR SEQUENCE FINISHED AT "
& IMAGE(now) & " !" & " *********"
severity note;
s_xor_end <= true;
wait;
end PROC_XOR;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- PROC_ADD - Test the logical ADD command --
-- --
-- Procedure to generate all the input data to test the logical --
-- ADD command. Furthermore the results are compared with the --
-- expected values and the simulation is stopped with an error message --
-- if the test failes. --
-----------------------------------------------------------------------------
procedure PROC_ADD (
constant DWIDTH : in positive;
constant PROP_DELAY : in time;
constant ADD_CARRY : in boolean;
signal s_cyi : in std_logic_vector;
signal s_ovi : in std_logic;
signal s_result : in std_logic_vector;
signal s_cyo : out std_logic_vector;
signal s_ovo : out std_logic;
signal s_operanda : out std_logic_vector;
signal s_operandb : out std_logic_vector;
signal s_add_end : out boolean) is
variable v_result : std_logic_vector(DWIDTH-1 downto 0);
variable v_flags : std_logic_vector((DWIDTH-1)/4+1 downto 0);
variable v_cyo : std_logic_vector(((DWIDTH-1)/4) downto 0);
variable v_ovo : std_logic;
variable v_carry : integer;
begin
s_add_end <= false;
for j in 0 to 2**DWIDTH-1 loop
s_operanda <= conv_std_logic_vector(j,DWIDTH);
for i in 0 to 2**DWIDTH-1 loop
s_operandb <= conv_std_logic_vector(i,DWIDTH);
for f in 0 to 2**(((DWIDTH-1)/4)+2)-1 loop
v_flags := conv_std_logic_vector(f,((DWIDTH-1)/4)+2);
s_cyo <= v_flags(((DWIDTH-1)/4) downto 0);
s_ovo <= v_flags(v_flags'HIGH);
v_carry := conv_integer(v_flags((DWIDTH-1)/4));
if ADD_CARRY = true then
for h in 0 to (DWIDTH-1)/4 loop
if DWIDTH > (h+1)*4 then
if (j mod 2**((h+1)*4) + i mod 2**((h+1)*4) + v_carry)
> 2**((h+1)*4)-1 then
v_cyo(h) := '1';
else
v_cyo(h) := '0';
end if;
else
if (j mod 2**(DWIDTH) + i mod 2**(DWIDTH) + v_carry
> 2**(DWIDTH)-1) then
v_cyo(h) := '1';
else
v_cyo(h) := '0';
end if;
end if;
end loop; -- h
-- if DWIDTH = 1 then
-- v_ovo := '0';
-- else
if (j+i > 2**DWIDTH-1
and (j mod 2**(DWIDTH-1) + i mod 2**(DWIDTH-1) + v_carry)
<= 2**(DWIDTH-1)-1) or
(j+i < 2**DWIDTH-1
and (j mod 2**(DWIDTH-1) + i mod 2**(DWIDTH-1) + v_carry)
> 2**(DWIDTH-1)-1) then
v_ovo := '1';
else
v_ovo := '0';
end if;
-- end if;
v_result := conv_std_logic_vector(j + i + v_carry,DWIDTH);
wait for PROP_DELAY;
assert (s_cyi = v_cyo)
and (s_ovi = v_ovo)
and (s_result = v_result)
report "ERROR in " & IMAGE(DWIDTH) & "bit ADDC operation!"
severity failure;
else
for h in 0 to (DWIDTH-1)/4 loop
if DWIDTH > (h+1)*4 then
if (j mod 2**((h+1)*4) + i mod 2**((h+1)*4))
> 2**((h+1)*4)-1 then
v_cyo(h) := '1';
else
v_cyo(h) := '0';
end if;
else
if (j mod 2**(DWIDTH) + i mod 2**(DWIDTH)
> 2**(DWIDTH)-1) then
v_cyo(h) := '1';
else
v_cyo(h) := '0';
end if;
end if;
end loop; -- h
-- if DWIDTH = 1 then
-- v_ovo := '0';
-- else
if (j+i > 2**DWIDTH-1
and (j mod 2**(DWIDTH-1) + i mod 2**(DWIDTH-1))
<= 2**(DWIDTH-1)-1) or
(j+i <= 2**DWIDTH-1
and (j mod 2**(DWIDTH-1) + i mod 2**(DWIDTH-1))
> 2**(DWIDTH-1)-1) then
v_ovo := '1';
else
v_ovo := '0';
end if;
-- end if;
v_result := conv_std_logic_vector(j+i,DWIDTH);
wait for PROP_DELAY;
assert (s_cyi = v_cyo)
and (s_ovi = v_ovo)
and (s_result = v_result)
report "ERROR in " & IMAGE(DWIDTH) & "bit ADD operation!"
severity failure;
end if;
end loop; -- f
end loop; -- i
end loop; -- j
assert false
report "********* " & IMAGE(DWIDTH)
& "BIT ADD SEQUENCE FINISHED AT "
& IMAGE(now) & " !" & " *********"
severity note;
s_add_end <= true;
wait;
end PROC_ADD;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- PROC_SUB - Test the logical SUB command --
-- --
-- Procedure to generate all the input data to test the --
-- SUB command. Furthermore the results are compared with the --
-- expected values and the simulation is stopped with an error message --
-- if the test failes. --
-----------------------------------------------------------------------------
procedure PROC_SUB (
constant DWIDTH : in positive;
constant PROP_DELAY : in time;
signal s_cyi : in std_logic_vector;
signal s_ovi : in std_logic;
signal s_result : in std_logic_vector;
signal s_cyo : out std_logic_vector;
signal s_ovo : out std_logic;
signal s_operanda : out std_logic_vector;
signal s_operandb : out std_logic_vector;
signal s_sub_end : out boolean) is
variable v_result : std_logic_vector(DWIDTH-1 downto 0);
variable v_flags : std_logic_vector((DWIDTH-1)/4+1 downto 0);
variable v_cyo : std_logic_vector(((DWIDTH-1)/4) downto 0);
variable v_ovo : std_logic;
variable v_carry : integer;
begin
s_sub_end <= false;
for j in 0 to 2**DWIDTH-1 loop
s_operanda <= conv_std_logic_vector(j,DWIDTH);
for i in 0 to 2**DWIDTH-1 loop
s_operandb <= conv_std_logic_vector(i,DWIDTH);
for f in 0 to 2**(((DWIDTH-1)/4)+2)-1 loop
v_flags := conv_std_logic_vector(f,((DWIDTH-1)/4)+2);
s_cyo <= v_flags(((DWIDTH-1)/4) downto 0);
s_ovo <= v_flags(v_flags'HIGH);
v_carry := conv_integer(v_flags((DWIDTH-1)/4));
for h in 0 to (DWIDTH-1)/4 loop
if DWIDTH > (h+1)*4 then
if (j mod 2**((h+1)*4) - i mod 2**((h+1)*4) - v_carry)
< 0 then
v_cyo(h) := '1';
else
v_cyo(h) := '0';
end if;
else
if (j mod 2**(DWIDTH) - i mod 2**(DWIDTH) - v_carry)
< 0 then
v_cyo(h) := '1';
else
v_cyo(h) := '0';
end if;
end if;
end loop; -- h
-- if DWIDTH = 1 then
-- v_ovo := '0';
-- else
if (j - i - v_carry < 0
and (j mod 2**(DWIDTH-1) - i mod 2**(DWIDTH-1) - v_carry)
>= 0) or
(j - i - v_carry >= 0
and (j mod 2**(DWIDTH-1) - i mod 2**(DWIDTH-1) - v_carry)
< 0) then
v_ovo := '1';
else
v_ovo := '0';
end if;
-- end if;
v_result := conv_std_logic_vector(j - i - v_carry,DWIDTH);
wait for PROP_DELAY;
assert (s_cyi = v_cyo)
and (s_ovi = v_ovo)
and (s_result = v_result)
report "ERROR in " & IMAGE(DWIDTH) & "bit SUB operation!"
severity failure;
end loop; -- f
end loop; -- i
end loop; -- j
assert false
report "********* " & IMAGE(DWIDTH)
& "BIT SUB SEQUENCE FINISHED AT "
& IMAGE(now) & " !" & " *********"
severity note;
s_sub_end <= true;
wait;
end PROC_SUB;
-----------------------------------------------------------------------------
constant PROP_DELAY : time := 100 ns;
constant MAX_DWIDTH : integer := 11;
type t_data_DA is array (1 to MAX_DWIDTH) of
std_logic_vector(MAX_DWIDTH-1 downto 0);
type t_cmd_DA is array (1 to MAX_DWIDTH) of std_logic_vector(5 downto 0);
type t_cy_DA is array (1 to MAX_DWIDTH) of
std_logic_vector((MAX_DWIDTH-1)/4 downto 0);
type t_ov_DA is array (1 to MAX_DWIDTH) of std_logic;
type t_end_DA is array (1 to MAX_DWIDTH) of boolean;
type t_data_DIV_ACC_RAM is array (1 to MAX_DWIDTH) of
std_logic_vector(MAX_DWIDTH-1 downto 0);
type t_cmd_DIV_ACC_RAM is array (1 to MAX_DWIDTH) of
std_logic_vector(5 downto 0);
type t_ov_DIV_ACC_RAM is array (1 to MAX_DWIDTH) of std_logic;
type t_end_DIV_ACC_RAM is array (1 to MAX_DWIDTH) of boolean;
type t_cy_DIV_ACC_RAM is array (1 to MAX_DWIDTH) of
std_logic_vector((MAX_DWIDTH-1)/4 downto 0);
type t_product_MUL_ACC_RAM is array (1 to MAX_DWIDTH) of
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