baseball_top.csf.rpt

用VHDL开发的棒球游戏

baseball_top - Quartus II Compilation Report File
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+-----------------------------------------------------------------------------------------+
| Report Information                                                                      |
+--------------------+--------------------------------------------------------------------+
| Project            | D:\CQ\book\CDROM_image\baseball\quartus/                           |
| Compiler Settings  | baseball_top                                                       |
| Quartus II Version | 2.2 Build 147 12/02/2002 SJ Web Edition                            |
+--------------------+--------------------------------------------------------------------+

Table of Contents
    Compilation Report
        Legal Notice
        Project Settings
            General Settings
        Results for "baseball_top" Compiler Settings
            Summary
            Compiler Settings
            Messages
            Hierarchy
            State Machines
                outcount:Inst_out_counter|sreg
                batlatch:Inst_batting_latch|sreg
                batting:Inst_batting|sreg
                base:Inst_base_state|sreg
                score:Inst_score_state|sreg
            Logic Options
            Synthesis Section
                Resource Utilization by Entity
            Device Options
            Floorplan View
            Resource Section
                Input Pins
                Output Pins
                All Package Pins
                Control Signals
                Global & Other Fast Signals
                Carry Chains
                Cascade Chains
                Non-Global High Fan-Out Signals
                Peripheral Signals
                LAB
                Local Routing Interconnect
                LAB External Interconnect
                Row Interconnect
                LAB Column Interconnect
                EAB Column Interconnect
                Resource Usage Summary
                Resource Utilization by Entity
                Delay Chain Summary
            Equations
            Pin-Out File
            Timing Analyses
                Timing Settings
                fmax (not incl. delays to/from pins)
                Register-to-Register fmax
                tsu (Input Setup Times)
                th (Input Hold Times)
                tco (Clock to Output Delays)
            Processing Time

+-----------------------------------------------------------------------------+
| Legal Notice                                                                |
+-----------------------------------------------------------------------------+
Copyright (C) 1991-2002 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.


+-----------------------------------------------------------------------------+
| General Settings                                                            |
+-----------------------------------------------------------------------------+
+-------------------+---------------------+
| Option            | Setting             |
+-------------------+---------------------+
| Start date & time | 04/03/2003 20:14:27 |
| Main task         | Compilation         |
| Settings name     | baseball_top        |
+-------------------+---------------------+

+-----------------------------------------------------------------------------+
| Summary                                                                     |
+-----------------------------------------------------------------------------+
+-------------------------------------+-----------------------------------------------+
| Processing status                   | Fitting Successful - Thu Apr 03 20:14:42 2003 |
| Timing requirements/analysis status | Circuit will not operate                      |
| Chip name                           | baseball_top                                  |
| Device for compilation              | EP1K10TC100-3                                 |
| Total logic elements                | 160 / 576 ( 27 % )                            |
| Total pins                          | 35 / 136 ( 25 % )                             |
| Total memory bits                   | 0 / 12,288 ( 0 % )                            |
| Total PLLs                          | 0 / 1 ( 0 % )                                 |
| Device for timing analysis          | EP1K10TC100-3                                 |
+-------------------------------------+-----------------------------------------------+

+-----------------------------------------------------------------------------+
| Compiler Settings                                                           |
+-----------------------------------------------------------------------------+
+----------------------------------------------------------+--------------------+
| Option                                                   | Setting            |
+----------------------------------------------------------+--------------------+
| Chip name                                                | baseball_top       |
| Family name                                              | ACEX1K             |
| Focus entity name                                        | |baseball_top      |
| Device                                                   | EP1K10TC100-3      |
| Disk space/compilation speed tradeoff                    | Normal             |
| Preserve fewer node names                                | On                 |
| Optimize timing                                          | Normal compilation |
| Optimize IOC register placement for timing               | On                 |
| Fast Fit compilation                                     | Off                |
| FIT_ONLY_ONE_ATTEMPT                                     | Off                |
| Perform WYSIWYG primitive resynthesis                    | Off                |
| Perform gate-level register retiming                     | Off                |
| Use Fitter timing information during synthesis           | Off                |
| Duplicate logic elements during fitting                  | Off                |
| Duplicate logic elements/resythesize LUTs during fitting | Off                |
| SignalProbe compilation                                  | Off                |
| Generate compressed bitstreams                           | Off                |