clk_div.vhd

用VHDL开发的棒球游戏

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity clk_div is
  
  generic (
    DIV_BITS : integer := 1);

  port (
    clk_in  : in  std_logic;
    clk_out : out std_logic);

end clk_div;

architecture rtl of clk_div is
signal div_dff : std_logic_vector(DIV_BITS-1 downto 0):= (others => '0');
begin  -- rtl

  process (clk_in)
  begin
    if clk_in'event and clk_in = '1' then  -- rising clock edge
      div_dff <= div_dff + 1;
    end if;
  end process;

  clk_out <= div_dff(DIV_BITS-1);
  
end rtl;