baseball_top_tb.vhd

用VHDL开发的棒球游戏

-- 栰媴僎乕儉梡僔儈儏儗乕僔儑儞儌僨儖
-- 偙偺僼傽僀儖傪Quartus偺僨僓僀儞偵擖傟側偄偱偔偩偝偄丅
-- 僐儞僷僀儖帪偵僄儔乕偑敪惗偟傑偡丅
LIBRARY  IEEE;
USE IEEE.std_logic_1164.all;
USE work.baseball_pkg.all;

LIBRARY ieee;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY testbench IS
END testbench;


ARCHITECTURE testbench_arch OF testbench IS
  COMPONENT baseball_top
    PORT (
      clk : in  std_logic;
      resetn : in  std_logic;
      hitn : in  std_logic;
      base1_led : out  std_logic;
      base2_led : out  std_logic;
      base3_led : out  std_logic;
      team0_led : out  std_logic;
      team1_led : out  std_logic;
      out_led1 : out  std_logic;
      out_led2 : out  std_logic;
      out_led3 : out  std_logic;
      score0_led : out  std_logic_vector (7 DOWNTO 0);
      score1_led : out  std_logic_vector (7 DOWNTO 0);
      batter_led : out  std_logic_vector (7 DOWNTO 0)
      );
  END COMPONENT;

  SIGNAL clk : std_logic;
  SIGNAL resetn : std_logic;
  SIGNAL hitn : std_logic;
  SIGNAL base1_led : std_logic;
  SIGNAL base2_led : std_logic;
  SIGNAL base3_led : std_logic;
  SIGNAL team0_led : std_logic;
  SIGNAL team1_led : std_logic;
  SIGNAL out_led1 : std_logic;
  SIGNAL out_led2 : std_logic;
  SIGNAL out_led3 : std_logic;
  SIGNAL score0_led : std_logic_vector (7 DOWNTO 0);
  SIGNAL score1_led : std_logic_vector (7 DOWNTO 0);
  SIGNAL batter_led : std_logic_vector (7 DOWNTO 0);

  constant CLK_CYCLE : time := 30 ns;
  constant DIV_BITS : integer := 15;
  
BEGIN
  baseball_unit : baseball_top PORT MAP (
    clk => clk,
    resetn => resetn,
    hitn => hitn,
    base1_led => base1_led,
    base2_led => base2_led,
    base3_led => base3_led,
    team0_led => team0_led,
    team1_led => team1_led,
    out_led1 => out_led1,
    out_led2 => out_led2,
    out_led3 => out_led3,
    score0_led => score0_led,
    score1_led => score1_led,
    batter_led => batter_led
    );

  process
  begin  -- process
    clk <= '0';
    wait for CLK_CYCLE/2;
    clk <= '1';
    wait for CLK_CYCLE/2;          
  end process;

  process
  begin  -- process
    resetn <= '0';
    wait for 2*CLK_CYCLE*2**DIV_BITS;
    resetn <= '1';
    wait;   
  end process;

  process
  begin  -- process
    hitn <= '1';
    wait for CLK_CYCLE*10*2**DIV_BITS;
    hitn <= '0';
    wait for CLK_CYCLE*2**DIV_BITS;
    hitn <= '1';
    wait for CLK_CYCLE*15*2**DIV_BITS;
    hitn <= '0';
    wait for CLK_CYCLE*2**DIV_BITS;
    hitn <= '1';
    wait for CLK_CYCLE*15*2**DIV_BITS;
    hitn <= '0';
    wait for CLK_CYCLE*2**DIV_BITS;
    hitn <= '1';
    wait for CLK_CYCLE*15*2**DIV_BITS;
    hitn <= '0';
    wait for CLK_CYCLE*2**DIV_BITS;
    hitn <= '1';
    wait for CLK_CYCLE*15*2**DIV_BITS;
    hitn <= '0';
    wait for CLK_CYCLE*2**DIV_BITS;
    hitn <= '1';
    wait for CLK_CYCLE*15*2**DIV_BITS;
    hitn <= '0';
    wait for CLK_CYCLE*2**DIV_BITS;
    hitn <= '1';
    wait for CLK_CYCLE*15*2**DIV_BITS;
    hitn <= '0';
    wait for CLK_CYCLE*2**DIV_BITS;
    hitn <= '1';
    wait for CLK_CYCLE*7*2**DIV_BITS;
    hitn <= '0';
    wait for CLK_CYCLE*2**DIV_BITS;
    hitn <= '1';
    wait for CLK_CYCLE*15*2**DIV_BITS;
    hitn <= '0';
    wait for CLK_CYCLE*2**DIV_BITS;
    hitn <= '1';
    wait for CLK_CYCLE*15*2**DIV_BITS;
    hitn <= '0';
    wait for CLK_CYCLE*2**DIV_BITS;
    hitn <= '1';
    wait for CLK_CYCLE*15*2**DIV_BITS;
    hitn <= '0';
    wait for CLK_CYCLE*2**DIV_BITS;
    hitn <= '1';
    wait for CLK_CYCLE*15*2**DIV_BITS;
    hitn <= '0';
    wait for CLK_CYCLE*2**DIV_BITS;
    hitn <= '1';
    wait for CLK_CYCLE*15*2**DIV_BITS;
    hitn <= '0';
    wait for CLK_CYCLE*2**DIV_BITS;
    hitn <= '1';
    wait for CLK_CYCLE*15*2**DIV_BITS;
    hitn <= '0';
    wait for CLK_CYCLE*2**DIV_BITS;
    hitn <= '1';
    wait for CLK_CYCLE*15*2**DIV_BITS;
    hitn <= '0';
    wait for CLK_CYCLE*2**DIV_BITS;
    hitn <= '1';
    wait for CLK_CYCLE*15*2**DIV_BITS;
    hitn <= '0';
    wait for CLK_CYCLE*2**DIV_BITS;
    hitn <= '1';
    wait for CLK_CYCLE*15*2**DIV_BITS;
    hitn <= '0';
    wait for CLK_CYCLE*2**DIV_BITS;
    hitn <= '1';
    wait for CLK_CYCLE*15*2**DIV_BITS;
    hitn <= '0';
    wait for CLK_CYCLE*2**DIV_BITS;
    hitn <= '1';
    wait;
    wait for CLK_CYCLE*10;
  end process;
END testbench_arch;

CONFIGURATION baseball_top_cfg OF testbench IS
  FOR testbench_arch
  END FOR;
END baseball_top_cfg;