batting.vhd

用VHDL开发的棒球游戏

library ieee;
use ieee.std_logic_1164.all;

entity batting is
	port (clk,active,resetn: in std_logic;
              hit1,hit2,hit3,hit4,out_out : out std_logic);
end;

architecture behavior of batting is
  type type_sreg is (fair,homerun,out0,out1,out2,out3,out4,out5,out6,out7,out8
                     ,three_base,two_base);
  signal sreg, next_sreg : type_sreg;
begin
  process (clk, resetn, next_sreg)
  begin
    if ( resetn='0' ) then
      sreg <= out8;
    elsif clk='1' and clk'event then
      sreg <= next_sreg;
    end if;
  end process;
  
  process (sreg,active)
  begin
    case sreg is
      when fair =>
        hit1<='1';
        hit2<='0';
        hit3<='0';
        hit4<='0';
        out_out<='0';
        if ( active='1' ) then
          next_sreg<=out3;
        else
          next_sreg<=fair;
        end if;
      when homerun =>
        hit1<='0';
        hit2<='0';
        hit3<='0';
        hit4<='1';
        out_out<='0';
        if ( active='1' ) then
          next_sreg<=out2;
        else
          next_sreg<=homerun;
        end if;
      when out0 =>
        hit1<='0';
        hit2<='0';
        hit3<='0';
        hit4<='0';
        out_out<='1';
        if ( active='1' ) then
          next_sreg<=out1;
        else
          next_sreg<=out0;
        end if;
      when out1 =>
        hit1<='0';
        hit2<='0';
        hit3<='0';
        hit4<='0';
        out_out<='1';
        if ( active='1' ) then
          next_sreg<=fair;
        else
          next_sreg<=out1;
        end if;
      when out2 =>
        hit1<='0';
        hit2<='0';
        hit3<='0';
        hit4<='0';
        out_out<='1';
        if ( active='1' ) then
          next_sreg<=out8;
        else
          next_sreg<=out2;
        end if;
      when out3 =>
        hit1<='0';
        hit2<='0';
        hit3<='0';
        hit4<='0';
        out_out<='1';
        if ( active='1' ) then
          next_sreg<=out4;
        else
          next_sreg<=out3;
        end if;
      when out4 =>
        hit1<='0';
        hit2<='0';
        hit3<='0';
        hit4<='0';
        out_out<='1';
        if ( active='1' ) then
          next_sreg<=out5;
        else
          next_sreg<=out4;
        end if;
      when out5 =>
        hit1<='0';
        hit2<='0';
        hit3<='0';
        hit4<='0';
        out_out<='1';
        if ( active='1' ) then
          next_sreg<=out6;
        else
          next_sreg<=out5;
        end if;
      when out6 =>
        hit1<='0';
        hit2<='0';
        hit3<='0';
        hit4<='0';
        out_out<='1';
        if ( active='1' ) then
          next_sreg<=out7;
        else
          next_sreg<=out6;
        end if;
      when out7 =>
        hit1<='0';
        hit2<='0';
        hit3<='0';
        hit4<='0';
        out_out<='1';
        if ( active='1' ) then
          next_sreg<=three_base;
        else
          next_sreg<=out7;
        end if;
      when out8 =>
        hit1<='0';
        hit2<='0';
        hit3<='0';
        hit4<='0';
        out_out<='1';
        if ( active='1' ) then
          next_sreg<=out0;
        else
          next_sreg<=out8;
        end if;
      when three_base =>
        hit1<='0';
        hit2<='0';
        hit3<='1';
        hit4<='0';
        out_out<='0';
        if ( active='1' ) then
          next_sreg<=two_base;
        else
          next_sreg<=three_base;
        end if;
      when two_base =>
        hit1<='0';
        hit2<='1';
        hit3<='0';
        hit4<='0';
        out_out<='0';
        if ( active='1' ) then
          next_sreg<=homerun;
        else
          next_sreg<=two_base;
        end if;
      when others => null;
    end case;
  end process;
end behavior;