outcount.vhd

用VHDL开发的棒球游戏

library ieee;
use ieee.std_logic_1164.all;

entity outcount is
	port (clk,out_in,resetn: in std_logic;
              change,out_led1,out_led2,out_led3 : out std_logic);
end;

architecture behavior of outcount is
  type type_sreg is (change_team,no_out,one_out,three_out,two_out);
  signal sreg, next_sreg : type_sreg;
begin
  process (clk, resetn)
  begin
    if resetn='0' then
      sreg <= no_out;
    elsif clk='1' and clk'event then
      sreg <= next_sreg;
    end if;
  end process;

  process (sreg,out_in)
  begin
    case sreg is
      when change_team =>
        out_led1<='0';
        out_led2<='0';
        out_led3<='0';

        next_sreg<=no_out;
        change<='0';
      when no_out =>
        out_led1<='1';
        out_led2<='1';
        out_led3<='1';
        if  out_in='1' then
          next_sreg<=one_out;
          change<='0';
        else
          next_sreg<=no_out;
          change<='0';
        end if;
      when one_out =>
        out_led1<='0';
        out_led2<='1';
        out_led3<='1';
        if out_in='1' then
          next_sreg<=two_out;
          change<='0';
        else
          next_sreg<=one_out;
          change<='0';
        end if;
      when three_out =>
        out_led1<='0';
        out_led2<='0';
        out_led3<='0';
        next_sreg<=change_team;
        change<='1';
      when two_out =>
        out_led1<='0';
        out_led2<='0';
        out_led3<='1';
        if out_in='1' then
          next_sreg<=three_out;
          change<='0';
        else
          next_sreg<=two_out;
          change<='0';
        end if;
      when others => null;
    end case;
  end process;
end behavior;