📄 score.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity score is
port (clk,base1,base2,base3,hit1,hit2,hit3,hit4,resetn: in std_logic;
add_to_score1,add_to_score2,add_to_score3,add_to_score4 : out std_logic);
end;
architecture behavior of score is
type type_sreg is (add1,add2,add3,add4,idle);
signal sreg, next_sreg : type_sreg;
signal next_add_to_score1,next_add_to_score2,next_add_to_score3,
next_add_to_score4 : std_logic;
begin
process (clk, resetn)
begin
if resetn='0' then
sreg <= idle;
add_to_score1 <= '0';
add_to_score2 <= '0';
add_to_score3 <= '0';
add_to_score4 <= '0';
elsif clk='1' and clk'event then
sreg <= next_sreg;
add_to_score1 <= next_add_to_score1;
add_to_score2 <= next_add_to_score2;
add_to_score3 <= next_add_to_score3;
add_to_score4 <= next_add_to_score4;
end if;
end process;
process (sreg,base1,base2,base3,hit1,hit2,hit3,hit4)
begin
case sreg is
when add1 =>
next_sreg<=idle;
next_add_to_score1<='0';
next_add_to_score2<='0';
next_add_to_score3<='0';
next_add_to_score4<='0';
when add2 =>
next_sreg<=idle;
next_add_to_score1<='0';
next_add_to_score2<='0';
next_add_to_score3<='0';
next_add_to_score4<='0';
when add3 =>
next_sreg<=idle;
next_add_to_score1<='0';
next_add_to_score2<='0';
next_add_to_score3<='0';
next_add_to_score4<='0';
when add4 =>
next_sreg<=idle;
next_add_to_score1<='0';
next_add_to_score2<='0';
next_add_to_score3<='0';
next_add_to_score4<='0';
when idle =>
if (((base1='0') and (base2='0') and (base3='0') and (hit4='1')) or
((base1='1') and (base2='0') and (base3='0') and (hit3='1')) or
((base1='0') and (base2='1') and (base3='0') and ((hit2='1') or ( hit3='1' ))) or
((base1='0') and (base2='0') and (base3='1') and ((hit1='1') or ( hit2='1' ) or ( hit3='1' ))) or
((base1='1') and (base2='1') and (base3='0') and (hit2='1')) or
((base1='1') and (base2='0') and (base3='1') and ((hit1='1') or (hit2='1'))) or
((base1='0') and (base2='1') and (base3='1') and (hit1='1')) or
((base1='1') and (base2='1') and (base3='1') and (hit1='1'))) then
next_sreg<=add1;
next_add_to_score2<='0';
next_add_to_score3<='0';
next_add_to_score4<='0';
next_add_to_score1<='1';
elsif (((base1='1') and (base2='0') and (base3='0') and (hit4='1')) or
((base1='0') and ( base2='1' ) and ( base3='0' ) and (hit4='1')) or
((base1='0') and ( base2='0' ) and ( base3='1' ) and (hit4='1')) or
(( base1='1' ) and ( base2='1' ) and ( base3='0' ) and (hit3='1')) or
(( base1='1' ) and ( base2='0' ) and ( base3='1' ) and (hit3='1')) or
(( base1='0' ) and ( base2='1' ) and ( base3='1' ) and (hit3='1')) or
(( base1='0' ) and ( base2='1' ) and ( base3='1' ) and (hit2='1')) or
(( base1='1' ) and ( base2='1' ) and ( base3='1' ) and (hit2='1'))) then
next_sreg<=add2;
next_add_to_score1<='0';
next_add_to_score3<='0';
next_add_to_score4<='0';
next_add_to_score2<='1';
elsif (((base1='1') and (base2='1') and (base3='0') and (hit4='1')) or
((base1='1') and (base2='0') and (base3='1') and (hit4='1')) or
(( base1='0') and (base2='1') and (base3='1') and (hit4='1')) or
((base1='1') and (base2='1') and (base3='1') and (hit3='1'))) then
next_sreg<=add3;
next_add_to_score1<='0';
next_add_to_score2<='0';
next_add_to_score4<='0';
next_add_to_score3<='1';
elsif ((base1='1') and (base2='1') and (base3='1') and (hit4='1')) then
next_sreg<=add4;
next_add_to_score1<='0';
next_add_to_score2<='0';
next_add_to_score3<='0';
next_add_to_score4<='1';
else
next_sreg<=idle;
next_add_to_score1<='0';
next_add_to_score2<='0';
next_add_to_score3<='0';
next_add_to_score4<='0';
end if;
when others => null;
end case;
end process;
end behavior;
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