baseball_top.vhd

用VHDL开发的棒球游戏

library IEEE;
use IEEE.std_logic_1164.all;

use work.baseball_pkg.all;

entity baseball_top is
  
  port (
    clk, resetn   : in  std_logic;
    hitn  : in  std_logic;    
    base1_led, base2_led, base3_led,
    team0_led, team1_led,out_led1, out_led2, out_led3: out std_logic;
    score0_led, score1_led,
    batter_led : out std_logic_vector(7 downto 0));

end baseball_top;

architecture rtl of baseball_top is
  COMPONENT base
    PORT(
      CLK : IN std_logic;
      hit1 : IN std_logic;
      hit2 : IN std_logic;
      hit3 : IN std_logic;
      hit4 : IN std_logic;
      resetn : IN std_logic;          
      base1 : OUT std_logic;
      base2 : OUT std_logic;
      base3 : OUT std_logic
      );
  END COMPONENT;

  COMPONENT baseball_led_out
    PORT(
      clk : IN std_logic;
      resetn : IN std_logic;
      team : IN std_logic;
      base1 : IN std_logic;
      base2 : IN std_logic;
      base3 : IN std_logic;
      add_to_score1 : IN std_logic;
      add_to_score2 : IN std_logic;
      add_to_score3 : IN std_logic;
      add_to_score4 : IN std_logic;          
      base1_led : OUT std_logic;
      base2_led : OUT std_logic;
      base3_led : OUT std_logic;
      team_led0, team_led1 : OUT std_logic;
      score0_led : OUT std_logic_vector(7 downto 0);
      score1_led : OUT std_logic_vector(7 downto 0)
      );
  END COMPONENT;
  
  COMPONENT batter_led_dec
    PORT(
      hit1 : IN std_logic;
      hit2 : IN std_logic;
      hit3 : IN std_logic;
      hit4 : IN std_logic;
      out_in : IN std_logic;          
      batter_led : OUT std_logic_vector(7 downto 0)
      );
  END COMPONENT;

  COMPONENT batting
    PORT(
      active : IN std_logic;
      clk : IN std_logic;
      resetn : IN std_logic;          
      hit1 : OUT std_logic;
      hit2 : OUT std_logic;
      hit3 : OUT std_logic;
      hit4 : OUT std_logic;
      out_out : OUT std_logic
      );
  END COMPONENT;
  COMPONENT batlatch
    PORT(
      clk : IN std_logic;
      hit1_in : IN std_logic;
      hit2_in : IN std_logic;
      hit3_in : IN std_logic;
      hit4_in : IN std_logic;
      out_in : IN std_logic;
      resetn : IN std_logic;
      start : IN std_logic;          
      hit1_out : OUT std_logic;
      hit2_out : OUT std_logic;
      hit3_out : OUT std_logic;
      hit4_out : OUT std_logic;
      out_out : OUT std_logic
      );
  END COMPONENT;
  COMPONENT outcount
    PORT(
      clk : IN std_logic;
      out_in : IN std_logic;
      resetn : IN std_logic;          
      change : OUT std_logic;
      out_led1 : OUT std_logic;
      out_led2 : OUT std_logic;
      out_led3 : OUT std_logic
      );
  END COMPONENT;
  COMPONENT score
    PORT(
      base1 : IN std_logic;
      base2 : IN std_logic;
      base3 : IN std_logic;
      clk : IN std_logic;
      hit1 : IN std_logic;
      hit2 : IN std_logic;
      hit3 : IN std_logic;
      hit4 : IN std_logic;
      resetn : IN std_logic;          
      add_to_score1 : OUT std_logic;
      add_to_score2 : OUT std_logic;
      add_to_score3 : OUT std_logic;
      add_to_score4 : OUT std_logic);
  END COMPONENT;
  
  COMPONENT clk_div 
  
  generic (DIV_BITS : integer := 1);

  port (
    clk_in  : in  std_logic;
    clk_out : out std_logic
  );
  end component;

  signal hit1_node1, hit2_node1, hit3_node1, hit4_node1, out_node1 : std_logic;
  signal hit1_node2, hit2_node2, hit3_node2, hit4_node2, out_node2 : std_logic;
  signal base1_node, base2_node, base3_node, add_to_score1_node, add_to_score2_node, add_to_score3_node, add_to_score4_node : std_logic;
  signal hitting_bit : std_logic := '0';
  signal change_ff, change_node, resetn_for_base_and_score : std_logic;
  signal clk_devided : std_logic;
  signal score0_led_node, score1_led_node : std_logic_vector(7 downto 0);
  signal team0_led_node, team1_led_node : std_logic;
  signal batter_led_node : std_logic_vector(7 downto 0);
  signal sw_latch, sw_latch_on : std_logic := '0';
  signal hitn_node : std_logic;
begin  -- rtl

  clk_divider : clk_div generic map (
    DIV_BITS => 15)
    port map (
      clk_in  => clk,
      clk_out => clk_devided);
  
  resetn_for_base_and_score <= '1' when resetn = '1' and change_node = '0' else
                               '0';

  Inst_score_state: score PORT MAP(
    clk => clk_devided,
    resetn => resetn_for_base_and_score,
    hit1 => hit1_node2,
    hit2 => hit2_node2,
    hit3 => hit3_node2,
    hit4 => hit4_node2,
    base1 => base1_node,
    base2 => base2_node,
    base3 => base3_node,
    add_to_score1 => add_to_score1_node,
    add_to_score2 => add_to_score2_node,
    add_to_score3 => add_to_score3_node,
    add_to_score4 => add_to_score4_node
    );

  Inst_base_state: base PORT MAP(
    clk => clk_devided,
    resetn => resetn_for_base_and_score,
    hit1 => hit1_node2,
    hit2 => hit2_node2,
    hit3 => hit3_node2,
    hit4 => hit4_node2,
    base1 => base1_node,
    base2 => base2_node,
    base3 => base3_node
    );

  Inst_baseball_led_out: baseball_led_out PORT MAP(
    clk => clk_devided,
    resetn => resetn,
    team => change_ff,
    base1 => base1_node,
    base2 => base2_node,
    base3 => base3_node,
    add_to_score1 => add_to_score1_node,
    add_to_score2 => add_to_score2_node,
    add_to_score3 => add_to_score3_node,
    add_to_score4 => add_to_score4_node,
    base1_led => base1_led,
    base2_led => base2_led,
    base3_led => base3_led,
    team_led0 => team0_led_node,
    team_led1 => team1_led_node,
    score0_led => score0_led_node,
    score1_led => score1_led_node
    );

  score0_led <= not score0_led_node;
  score1_led <= not score1_led_node;
  
  -- 僇僜乕僪僐儌儞偺偨傔偺榑棟斀揮
  team0_led <= not team0_led_node;
  team1_led <= not team1_led_node;

  Inst_batter_led_dec: batter_led_dec PORT MAP(
    hit1 => hit1_node1,
    hit2 => hit2_node1,
    hit3 => hit3_node1,
    hit4 => hit4_node1,
    out_in => out_node1,
    batter_led => batter_led_node
    );

  batter_led <= not batter_led_node;

  Inst_batting: batting PORT MAP(
    clk => clk_devided,
    resetn => resetn,
    active => hitting_bit,
    hit1 => hit1_node1,
    hit2 => hit2_node1,
    hit3 => hit3_node1,
    hit4 => hit4_node1,
    out_out => out_node1
    );

  -- 僠儍僞儕儞僌彍嫀夞楬
  process (clk_devided)
  begin  -- process
    if clk_devided'event and clk_devided = '1' then  -- rising clock edge
      hitn_node <= hitn;
    end if;
  end process;

  -- 僸僢僩僗僀僢僠擖椡偐傜懪寕儖乕儗僢僩偺僆儞丒僆僼偺僩僌儖傪偡傞
  -- DFF傪惂屼偡傞夞楬
  -- 僠儍僞儕儞僌彍嫀偟偨偁偲偺hitn擖椡傪巊偆
  process (clk, resetn)
  begin  -- process
    if resetn = '0' then
      hitting_bit <= '0';
      sw_latch_on <= '0';
    elsif clk'event and clk = '1' then  -- rising clock edge
      if hitn_node = '0' and sw_latch_on = '0' then
        hitting_bit <= not hitting_bit;        
        sw_latch_on <= '1';
      elsif hitn_node = '1' and sw_latch_on = '1' then
        sw_latch_on <= '0';
      elsif hitn_node = '0' and sw_latch_on = '1' then
        sw_latch_on <= '1';
      end if;
    end if;
  end process;

  -- 峌寕僠乕儉傪娗棟偡傞僩僌儖丒儔僢僠
  process (change_node, resetn)
  begin  -- process
    if resetn = '0' then                -- asynchronous reset (active low)
      change_ff <= '0';
    elsif change_node'event and change_node = '1' then  -- rising clock edge
      change_ff <= not change_ff;
    end if;
  end process;

  Inst_batting_latch: batlatch PORT MAP(
    clk => clk_devided,
    resetn => resetn,
    hit1_in => hit1_node1,
    hit2_in => hit2_node1,
    hit3_in => hit3_node1,
    hit4_in => hit4_node1,
    out_in => out_node1,
    start => hitting_bit,
    hit1_out => hit1_node2,
    hit2_out => hit2_node2,
    hit3_out => hit3_node2,
    hit4_out => hit4_node2,
    out_out => out_node2
    );
  Inst_out_counter: outcount PORT MAP(
    clk => clk_devided,
    out_in => out_node2,
    resetn => resetn,
    change => change_node,
    out_led1 => out_led1,
    out_led2 => out_led2,
    out_led3 => out_led3
    );

  
end rtl;