dds.tan.summary

直接数字式频率合成器(DDS)设计实验(电子设计竞赛赛题) 其它详细资料说明请参考 http://www.kx-soc.com

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.583 ns
From           : FWORD[0]
To             : REG32B:u2|DOUT[31]
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.089 ns
From           : SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_qqs:auto_generated|altsyncram_kna2:altsyncram1|ram_block3a9~porta_address_reg9
To             : FOUT[8]
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 4.993 ns
From           : CLK
To             : DA_CLK
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.330 ns
From           : altera_internal_jtag
To             : sld_signaltap:dds1|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[53]
From Clock     : 
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.105 ns
From           : SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_qqs:auto_generated|altsyncram_kna2:altsyncram1|ram_block3a6~porta_address_reg9
To             : FOUT[3]
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Worst-case Minimum tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.124 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 108.08 MHz ( period = 9.252 ns )
From           : sld_signaltap:dds1|sld_rom_sr:crc_rom_sr|WORD_SR[0]
To             : sld_hub:sld_hub_inst|HUB_TDO~reg0
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 149.28 MHz ( period = 6.699 ns )
From           : SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_qqs:auto_generated|altsyncram_kna2:altsyncram1|ram_block3a9~porta_address_reg9
To             : sld_signaltap:dds1|acq_trigger_in_reg[8]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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