reg32b.vhd

来自「直接数字式频率合成器(DDS)设计实验(电子设计竞赛赛题) 其它详细资料说明请参」· VHDL 代码 · 共 17 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG32B IS
    PORT (  Load : IN STD_LOGIC;
             DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
            DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );
END REG32B;
ARCHITECTURE behav OF REG32B IS
BEGIN
    PROCESS(Load, DIN)
   BEGIN
   IF Load'EVENT AND Load = '1' THEN DOUT <= DIN; END IF;
    END PROCESS;
END behav;