songer.tan.rpt

VHDL计数器

; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Minimum tpd to report                                 ; 0.0NS              ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; Off                ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                       ;
+------------------------------+-------+---------------+------------------------------------------------+---------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From                                                                                  ; To                                                                                     ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+---------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 38.700 ns                                      ; NoteTabs:u1|lpm_counter:Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]             ; CODE1[0]                                                                               ; CLK8HZ     ;          ; 0            ;
; Worst-case Minimum tco       ; N/A   ; None          ; 19.300 ns                                      ; NoteTabs:u1|lpm_counter:Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]             ; HIGH1                                                                                  ; CLK8HZ     ;          ; 0            ;
; Clock Setup: 'CLK12MHZ'      ; N/A   ; None          ; 71.43 MHz ( period = 14.000 ns )               ; Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[6] ; Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[10] ; CLK12MHZ   ; CLK12MHZ ; 0            ;
; Clock Setup: 'CLK8HZ'        ; N/A   ; None          ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; NoteTabs:u1|lpm_counter:Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]             ; NoteTabs:u1|lpm_counter:Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]              ; CLK8HZ     ; CLK8HZ   ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                                                                                       ;                                                                                        ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+---------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; CLK8HZ          ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; CLK12MHZ        ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK8HZ'                                                                                                                                                                                                                                                                                                      ;
+-------+------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                      ; To                                                                        ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; NoteTabs:u1|lpm_counter:Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; NoteTabs:u1|lpm_counter:Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; CLK8HZ     ; CLK8HZ   ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; NoteTabs:u1|lpm_counter:Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; NoteTabs:u1|lpm_counter:Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; CLK8HZ     ; CLK8HZ   ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; NoteTabs:u1|lpm_counter:Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; NoteTabs:u1|lpm_counter:Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; CLK8HZ     ; CLK8HZ   ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; NoteTabs:u1|lpm_counter:Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; NoteTabs:u1|lpm_counter:Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; CLK8HZ     ; CLK8HZ   ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; NoteTabs:u1|lpm_counter:Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; NoteTabs:u1|lpm_counter:Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; CLK8HZ     ; CLK8HZ   ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; NoteTabs:u1|lpm_counter:Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; NoteTabs:u1|lpm_counter:Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; CLK8HZ     ; CLK8HZ   ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; NoteTabs:u1|lpm_counter:Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; NoteTabs:u1|lpm_counter:Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; CLK8HZ     ; CLK8HZ   ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; NoteTabs:u1|lpm_counter:Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; NoteTabs:u1|lpm_counter:Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; CLK8HZ     ; CLK8HZ   ; None                        ; None                      ; None                    ;