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📄 songer.map.rpt

📁 VHDL计数器
💻 RPT
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; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in G:/EP1C6_10_1_SONGER/SONGER.map.eqn.


+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                              ;
+-------------------------------------------------------------------+-----------------+
; File Name                                                         ; Used in Netlist ;
+-------------------------------------------------------------------+-----------------+
; notetabs.vhd                                                      ; yes             ;
; tonetaba.vhd                                                      ; yes             ;
; speakera.vhd                                                      ; yes             ;
; songer.vhd                                                        ; yes             ;
; e:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf       ; yes             ;
; e:/altera/quartus41/libraries/megafunctions/lpm_constant.inc      ; yes             ;
; e:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf ; yes             ;
; e:/altera/quartus41/libraries/megafunctions/flex10ke_lcell.inc    ; yes             ;
+-------------------------------------------------------------------+-----------------+


+---------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                                   ;
+-----------------------------------+---------------------------------------------------------------------------+
; Resource                          ; Usage                                                                     ;
+-----------------------------------+---------------------------------------------------------------------------+
; Logic cells                       ; 122                                                                       ;
; Total combinational functions     ; 120                                                                       ;
; Total 4-input functions           ; 88                                                                        ;
; Total 3-input functions           ; 5                                                                         ;
; Total 2-input functions           ; 3                                                                         ;
; Total 1-input functions           ; 1                                                                         ;
; Total 0-input functions           ; 23                                                                        ;
; Combinational cells for routing   ; 0                                                                         ;
; Total registers                   ; 25                                                                        ;
; Total logic cells in carry chains ; 23                                                                        ;
; I/O pins                          ; 8                                                                         ;
; Maximum fan-out node              ; NoteTabs:u1|lpm_counter:Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ;
; Maximum fan-out                   ; 44                                                                        ;
; Total fan-out                     ; 462                                                                       ;
; Average fan-out                   ; 3.55                                                                      ;
+-----------------------------------+---------------------------------------------------------------------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 23    ;
; Number of synthesis-generated cells                    ; 99    ;
; Number of WYSIWYG LUTs                                 ; 23    ;
; Number of synthesis-generated LUTs                     ; 97    ;
; Number of WYSIWYG registers                            ; 23    ;
; Number of synthesis-generated registers                ; 2     ;
; Number of cells with combinational logic only          ; 97    ;
; Number of cells with registers only                    ; 2     ;
; Number of cells with combinational logic and registers ; 23    ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 11    ;
; Number of registers using Asynchronous Clear ; 12    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Sat Jun 04 11:22:32 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off SONGER -c SONGER
Info: Found 2 design units, including 1 entities, in source file notetabs.vhd
    Info: Found design unit 1: NoteTabs-one
    Info: Found entity 1: NoteTabs
Info: Found 2 design units, including 1 entities, in source file tonetaba.vhd
    Info: Found design unit 1: ToneTaba-one
    Info: Found entity 1: ToneTaba
Info: Found 2 design units, including 1 entities, in source file speakera.vhd
    Info: Found design unit 1: Speakera-one
    Info: Found entity 1: Speakera
Info: Found 2 design units, including 1 entities, in source file songer.vhd
    Info: Found design unit 1: Songer-one
    Info: Found entity 1: Songer
Warning: VHDL Process Statement warning at notetabs.vhd(12): signal counter is in statement, but is not in sensitivity list
Info: VHDL Case Statement information at notetabs.vhd(233): OTHERS choice is never selected
Warning: VHDL Process Statement warning at tonetaba.vhd(11): signal or variable tone may not be assigned a new value in every possible path through the Process Statement. Signal or variable tone holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at tonetaba.vhd(11): signal or variable code may not be assigned a new value in every possible path through the Process Statement. Signal or variable code holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at tonetaba.vhd(11): signal or variable high may not be assigned a new value in every possible path through the Process Statement. Signal or variable high holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: LATCH primitive ToneTaba:u2|CODE[3] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|CODE[2] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|CODE[1] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|CODE[0] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|HIGH is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[10] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[9] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[8] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[7] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[6] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[5] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[4] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[3] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[2] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[1] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[0] is permanently enabled
Info: Inferred 3 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: NoteTabs:u1|Counter[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=11) from the following logic: Speakera:u3|\GenSpkS:Count11[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: Speakera:u3|\DivideCLK:Count4[0]~0
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Ignored 15 buffer(s)
    Info: Ignored 15 SOFT buffer(s)
Info: Duplicate registers merged to single register
    Info: Duplicate register Speakera:u3|\DelaySpkS:Count2 merged to single register Speakera:u3|SpkS
Warning: Output pins are stuck at VCC or GND
    Warning: Pin CODE1[3] stuck at GND
Info: Implemented 130 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 6 output pins
    Info: Implemented 122 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 22 warnings
    Info: Processing ended: Sat Jun 04 11:22:35 2005
    Info: Elapsed time: 00:00:03


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