command.log

8051的内核(vhdl) This is version 1.1. of the MC8051 IP core. 在FPGA上运行.供有精力的人研究.

mgi_scratch_directory = "."
multi_pass_test_generation = "false"
pla_read_create_flip_flop = "false"
plot_box = "false"
plot_command = "lpr -Plw"
plot_orientation = "best_fit"
plot_scale_factor = 100
plotter_maxx = 584
plotter_maxy = 764
plotter_minx = 28
plotter_miny = 28
port_complement_naming_style = "%s_BAR"
power_gated_clock_logic = "and buf"
power_keep_license_after_power_commands = "false"
power_preserve_rtl_hier_names = "false"
power_reg_size_threshold = 3
power_rtl_saif_file = "power_rtl.saif"
power_sdpd_saif_file = "power_sdpd.saif"
power_test_enable = "false"
power_test_enable_pin = "TEST_MODE"
power_test_obs_logic = "false"
power_test_obs_logic_depth = 5
read_db_lib_warnings = "FALSE"
read_name_mapping_nowarn_libraries = {}
read_translate_msff = "TRUE"
reoptimize_design_changed_list_file_name = ""
sdfin_fall_cell_delay_type = "maximum"
sdfin_fall_net_delay_type = "maximum"
sdfin_min_fall_cell_delay = 0.000000
sdfin_min_fall_net_delay = 0.000000
sdfin_min_rise_cell_delay = 0.000000
sdfin_min_rise_net_delay = 0.000000
sdfin_rise_cell_delay_type = "maximum"
sdfin_rise_net_delay_type = "maximum"
sdfin_top_instance_name = ""
sdfout_allow_non_positive_constraints = "false"
sdfout_min_fall_cell_delay = 0.000000
sdfout_min_fall_net_delay = 0.000000
sdfout_min_rise_cell_delay = 0.000000
sdfout_min_rise_net_delay = 0.000000
sdfout_time_scale = 1.000000
sdfout_top_instance_name = ""
sdfout_write_to_output = "false"
search_path = {".", "/home/mietec/ads98.1/cmos035/v1.8/syn98.2", "/home/synopsys.9910/libraries/syn"}
sh_command_abbrev_mode = "Anywhere"
sh_continue_on_error = "true"
sh_enable_page_mode = "true"
sh_source_uses_search_path = "true"
single_group_per_sheet = "false"
site_info_file = "/home/synopsys.9910/admin/license/site_info"
sort_outputs = "false"
suppress_errors = {"PWR-18", "OPT-931", "OPT-932"}
symbol_library = {"MTC45000.sdb"}
synlib_disable_limited_licenses = "true"
synlib_dont_get_license = {}
synlib_evaluation_mode = "false"
synlib_model_map_effort = "medium"
synlib_optimize_non_cache_elements = "true"
synlib_prefer_ultra_license = "false"
synlib_preferred_library = {}
synlib_sequential_module = "default"
synlib_wait_for_design_license = {}
synopsys = "/home/synopsys.9910"
syntax_check_status = "false"
synthetic_library = {"standard.sldb"}
target_library = {"MTC45000.db", "MTC45000_WL_WORST.db"}
tdlout_upcase = "true"
template_naming_style = "%s_%p"
template_parameter_style = "%s%d"
template_separator_style = "_"
test_allow_clock_reconvergence = "true"
test_bsd_allow_tolerable_violations = "false"
test_bsd_control_cell_drive_limit = 0
test_bsd_manufacturer_id = 0
test_bsd_optimize_control_cell = "false"
test_bsd_part_number = 0
test_bsd_version_number = 0
test_bsdl_default_suffix_name = "bsdl"
test_bsdl_max_line_length = 80
test_capture_clock_skew = "small_skew"
test_cc_ir_masked_bits = 0
test_cc_ir_value_of_masked_bits = 0
test_check_port_changes_in_capture = "true"
test_clock_port_naming_style = "test_c%s"
test_dedicated_subdesign_scan_outs = "true"
test_default_bidir_delay = 55.000000
test_default_delay = 5.000000
test_default_min_fault_coverage = 95
test_default_period = 100.000000
test_default_scan_style = "multiplexed_flip_flop"
test_default_strobe = 95.000000
test_default_strobe_width = 0.000000
test_design_analyzer_uses_insert_scan = "true"
test_disable_find_best_scan_out = "false"
test_disconnect_non_functional_so = 1
test_dont_fix_constraint_violations = "false"
test_infer_slave_clock_pulse_after_capture = "infer"
test_isolate_hier_scan_out = 0
test_mode_port_inverted_naming_style = "test_mode_i%s"
test_mode_port_naming_style = "test_mode%s"
test_non_scan_clock_port_naming_style = "test_nsc_%s"
test_preview_scan_shows_cell_types = "false"
test_protocol_add_cycle = "true"
test_scan_clock_a_port_naming_style = "test_sca%s"
test_scan_clock_b_port_naming_style = "test_scb%s"
test_scan_clock_port_naming_style = "test_sc%s"
test_scan_enable_inverted_port_naming_style = "test_sei%s"
test_scan_enable_port_naming_style = "test_se%s"
test_scan_in_port_naming_style = "test_si%s%s"
test_scan_link_so_lockup_key = "l"
test_scan_link_wire_key = "w"
test_scan_out_port_naming_style = "test_so%s%s"
test_scan_segment_key = "s"
test_scan_true_key = "t"
test_stil_multiclock_capture_procedures = "false"
test_stil_netlist_format = "db"
test_user_defined_instruction_naming_style = "USER%d"
test_user_test_data_register_naming_style = "UTDR%d"
test_write_four_cycle_stil_protocol = "false"
testsim_print_stats_file = "true"
text_editor_command = "xterm -fn 8x13 -e vi %s &"
text_print_command = "lpr -Plw"
timing_self_loops_no_skew = "false"
true_delay_prove_false_backtrack_limit = 1000
true_delay_prove_true_backtrack_limit = 1000
uniquify_naming_style = "%s_%d"
use_port_name_for_oscs = "true"
verbose_messages = "true"
verilogout_debug_mode = "false"
verilogout_equation = "false"
verilogout_higher_designs_first = "FALSE"
verilogout_ignore_case = "false"
verilogout_include_files = {}
verilogout_levelize = "FALSE"
verilogout_no_negative_index = "FALSE"
verilogout_no_tri = "false"
verilogout_show_unconnected_pins = "FALSE"
verilogout_single_bit = "false"
verilogout_unconnected_prefix = "SYNOPSYS_UNCONNECTED_"
vhdllib_architecture = {"UDSM", "FTSM", "FTGS", "VITAL"}
vhdllib_glitch_handle = "true"
vhdllib_logic_system = "ieee-1164"
vhdllib_logical_name = ""
vhdllib_negative_constraint = "false"
vhdllib_pulse_handle = "use_vhdllib_glitch_handle"
vhdllib_tb_compare = 0
vhdllib_tb_x_eq_dontcare = "FALSE"
vhdllib_timing_checks = "true"
vhdllib_timing_mesg = "true"
vhdllib_timing_xgen = "false"
vhdlout_architecture_name = "SYN_%a_%u"
vhdlout_bit_type = "std_logic"
vhdlout_bit_type_resolved = "TRUE"
vhdlout_bit_vector_type = "std_logic_vector"
vhdlout_conversion_functions = {}
vhdlout_debug_mode = "false"
vhdlout_dont_create_dummy_nets = "FALSE"
vhdlout_dont_write_types = "FALSE"
vhdlout_equations = "FALSE"
vhdlout_follow_vector_direction = "FALSE"
vhdlout_levelize = "FALSE"
vhdlout_one_name = "'1'"
vhdlout_package_naming_style = "CONV_PACK_%d"
vhdlout_preserve_hierarchical_types = "VECTOR"
vhdlout_separate_scan_in = "FALSE"
vhdlout_single_bit = "USER"
vhdlout_synthesis_off = "TRUE"
vhdlout_target_simulator = ""
vhdlout_three_state_name = "'Z'"
vhdlout_three_state_res_func = ""
vhdlout_time_scale = 1.000000
vhdlout_top_configuration_arch_name = "A"
vhdlout_top_configuration_entity_name = "E"
vhdlout_top_configuration_name = "CFG_TB_E"
vhdlout_unknown_name = "'X'"
vhdlout_upcase = "FALSE"
vhdlout_use_packages = {"IEEE.std_logic_1164"}
vhdlout_wired_and_res_func = ""
vhdlout_wired_or_res_func = ""
vhdlout_write_architecture = "TRUE"
vhdlout_write_components = "TRUE"
vhdlout_write_entity = "TRUE"
vhdlout_write_top_configuration = "FALSE"
vhdlout_zero_name = "'0'"
view_analyze_file_suffix = {"v", "vhd", "vhdl"}
view_arch_types = {"apollo", "decmips", "hp700", "mips", "necmips", "rs6000", "sgimips", "sonymips", "sun3", "sparc"}
view_background = "black"
view_cache_images = "true"
view_command_log_file = "./view_command.log"
view_command_win_max_lines = 1000
view_dialogs_modal = "true"
view_disable_cursor_warping = "true"
view_disable_error_windows = "false"
view_disable_output = "false"
view_error_window_count = 6
view_execute_script_suffix = {".script", ".scr", ".dcs", ".dcv", ".dc", ".con"}
view_info_search_cmd = "/home/synopsys.9910/infosearch/scripts/InfoSearch"
view_log_file = ""
view_on_line_doc_cmd = "/home/synopsys.9910/sold"
view_read_file_suffix = {"db", "gdb", "sdb", "edif", "eqn", "fnc", "lsi", "mif", "NET", "pla", "st", "tdl", "v", "vhd", "vhdl", "xnf"}
view_script_submenu_items = {"DA to SGE Transfer", "write_sge"}
view_tools_menu_items = {}
view_use_small_cursor = ""
view_use_x_routines = "true"
view_write_file_suffix = {"gdb", "db", "sdb", "do", "edif", "eqn", "fnc", "lsi", "NET", "neted", "pla", "st", "tdl", "v", "vhd", "vhdl", "xnf"}
write_name_mapping_nowarn_libraries = {}
write_name_nets_same_as_ports = "false"
write_test_formats = {"synopsys", "tssi_ascii", "tds", "verilog", "vhdl", "wgl"}
write_test_include_scan_cell_info = "true"
write_test_input_dont_care_value = "X"
write_test_max_cycles = 0
write_test_max_scan_patterns = 0
write_test_pattern_set_naming_style = "TC_Syn_%d"
write_test_round_timing_values = "true"
write_test_scan_check_file_naming_style = "%s_schk.%s"
write_test_vector_file_naming_style = "%s_%d.%s"
x11_set_cursor_background = ""
x11_set_cursor_foreground = ""
x11_set_cursor_number = -1
xnfin_dff_clock_enable_pin_name = "CE"
xnfin_dff_clock_pin_name = "C"
xnfin_dff_data_pin_name = "D"
xnfin_dff_q_pin_name = "Q"
xnfin_dff_reset_pin_name = "RD"
xnfin_dff_set_pin_name = "SD"
xnfin_family = "4000"
xnfin_ignore_pins = "GTS GSR GR"
xnfout_clock_attribute_style = "CLK_ONLY"
xnfout_constraints_per_endpoint = "50"
xnfout_default_time_constraints = "true"
xnfout_library_version = ""
xterm_executable = "xterm"


/* Initial dc_shell Aliases */


alias analyze_scan 	"preview_scan"
alias check_clocks 	"check_timing"
alias compile_inplace_changed_list_file_name 	"reoptimize_design_changed_list_file_name"
alias compile_test 	"insert_test"
alias create_test_vectors 	"create_test_patterns"
alias disable_timing 	"set_disable_timing"
alias dont_touch   	"set_dont_touch"
alias dont_touch_network 	"set_dont_touch_network"
alias dont_use     	"set_dont_use"
alias est_resource_preference 	"estimate_resource_preference"
alias fix_hold     	"set_fix_hold"
alias free         	"remove_design"
alias fsm_minimize 	"minimize_fsm"
alias fsm_reduce   	"reduce_fsm"
alias gen          	"create_schematic"
alias group_bus    	"create_bus"
alias groupvar     	"group_variable"
alias hist         	"history"
alias lint         	"check_design"
alias list_duplicate_designs 	"include -quiet ldd_script; dc_shell_status = ldd_return_val "
alias ls           	"sh ls -aC "
alias man          	"help"
alias prefer       	"set_prefer"
alias remove_package 	"echo remove_package command is obsolete: packages are stored on disk not in-memory:"
alias report_attributes 	"report_attribute"
alias report_clock_constraint 	"report_timing -path end -to all_registers(-data_pins)"
alias report_clock_tree 	"report_transitive_fanout -clock_tree"
alias report_clocks 	"report_clock"
alias report_constraints 	"report_constraint"
alias report_register 	"report_timing_requirements;report_clock -skew"
alias report_synthetic 	"report_cell"
alias set_connect_delay 	"set_annotated_delay -net"
alias set_internal_arrival 	"set_arrival"
alias set_internal_load 	"set_load"
alias set_ultra_mode 	"set_ultra_optimization"
alias site_info    	"sh cat site_info_file"
alias ungroup_bus  	"remove_bus"
alias verify       	"compare_design"
alias view_cursor_number 	"x11_set_cursor_number"
alias write_sge    	"include db2sge_script"


/* dc_shell Command Log */ 


/* --------------------------------------------------------------------- */ 
/* This is the synthesis script for the 8051 microcontroller-conrolunit  */ 
/* --------------------------------------------------------------------- */ 
sh date 
sh hostname 
main_module = mc8051_core 
file_list = {mc8051_p, \
             control_fsm_, \
             control_fsm_rtl, \
             control_mem_, \
             control_mem_rtl, \
             mc8051_control_, \
             mc8051_control_struc, \
             alucore_, \
             alucore_rtl, \
             alumux_, \
             alumux_rtl, \
             addsub_cy_, \
             addsub_cy_rtl, \
             addsub_ovcy_, \
             addsub_ovcy_rtl, \
             addsub_core_, \
             addsub_core_struc, \
             comb_divider_, \
             comb_divider_rtl, \
             comb_mltplr_, \
             comb_mltplr_rtl, \
             dcml_adjust_, \
             dcml_adjust_rtl, \
             mc8051_alu_, \
             mc8051_alu_struc, \
             mc8051_siu_, \
             mc8051_siu_rtl, \
             mc8051_tmrctr_, \
             mc8051_tmrctr_rtl, \
             mc8051_core_, \
             mc8051_core_struc}    
db_area = "./db/" 
vhd_area = "../vhdl/" 
report_area = "./reports/" 
script_area = "./scr/" 
foreach (member, file_list) { 
   analyze -format vhdl vhd_area + member + ".vhd" 
   if (dc_shell_status == 0) { 
      echo "ANALYSIS ERROR OR FILE " member " NOT FOUND" 
      quit 
   } 
} 
elaborate main_module -update 
check_design 
write -f db -h -o db_area + main_module + "_pre.db" 
uniquify 
ungroup -all -flatten 
current_design = main_module 
create_clock -period 100 -waveform {0 50} -name clk clk 
set_clock_skew -ideal {clk} 
set_dont_touch_network {clk}  
/* Compile the design and write database */ 
check_design 
compile 
write -f db -h -o db_area + main_module + ".db" 
write -format vhdl -hierarchy -output db_area + main_module + ".vhd" 
check_design 
/* Generate reports */ 
report_area > report_area + main_module + ".area" 
report_timing > report_area + main_module + ".time" 
report_cell > report_area + main_module + ".cell" 
sh date 
quit