command.log

8051的内核(vhdl) This is version 1.1. of the MC8051 IP core. 在FPGA上运行.供有精力的人研究.

/* hydrogen -- Sat Dec 22 11:54:11 2001
   Initial dc_shell Variable Values */


_bs_arch = "sparcOS5"
_bs_suppress_errors = {"PWR-18", "OPT-931", "OPT-932"}
_bs_valid_program = "true"
acs_area_report_suffix = "area"
acs_bs_exec = ""
acs_budget_output_file_suffix = "btcl.out"
acs_budget_script_file_suffix = "btcl"
acs_budgeted_cstr_suffix = "con"
acs_compile_script_suffix = "autoscr"
acs_constraint_file_suffix = "con"
acs_cstr_report_suffix = "cstr"
acs_db_suffix = "db"
acs_dc_exec = ""
acs_global_user_compile_strategy_script = "default.compile"
acs_log_file_suffix = "log"
acs_makefile_name = "Makefile"
acs_num_parallel_jobs = "1"
acs_override_script_suffix = "scr"
acs_qor_report_suffix = "qor"
acs_script_mode = "dcsh"
acs_timing_report_suffix = "tim"
acs_tr_exec = ""
acs_use_lsf = "false"
acs_user_budgeting_script = "budget.scr"
acs_user_compile_strategy_script_suffix = "compile"
acs_work_dir = "/a/ursus/hoeller/mc8051/dc"
atpg_bidirect_output_only = "false"
atpg_test_asynchronous_pins = "true"
auto_link_disable = "false"
auto_link_options = "-all"
auto_wire_load_selection = "true"
bc_allow_shared_memories = "false"
bc_chain_read_into_mem = "true"
bc_chain_read_into_oper = "true"
bc_constrain_signal_memories = "false"
bc_detect_array_accesses = "false"
bc_detect_memory_accesses = "false"
bc_enable_analysis_info = "false"
bc_enable_chaining = "true"
bc_enable_multi_cycle = "true"
bc_enable_speculative_execution = "false"
bc_estimate_mux_input = 4
bc_estimate_timing_effort = "high"
bc_fsm_coding_style = "one_hot"
bc_group_eql_logic = "true"
bc_group_index_logic = "true"
bc_infer_multibit = "false"
bc_minimum_multibit_component_width = 4
bc_report_filter = ""
bc_time_all_sequential_op_bindings = "false"
bc_use_registerfiles = "false"
bin_path = "/home/synopsys.9910/sparcOS5/syn/bin"
bus_dimension_separator_style = "><"
bus_extraction_style = "%s[%d:%d]"
bus_inference_descending_sort = "true"
bus_inference_style = "%s<%d>"
bus_minus_style = "-%d"
bus_multiple_separator_style = ","
bus_naming_style = "%s<%d>"
bus_range_separator_style = ":"
cache_dir_chmod_octal = "777"
cache_file_chmod_octal = "666"
cache_read = {"/home/synopsys.9910/"}
cache_read_info = "false"
cache_write = "/home/synopsys.9910/"
cache_write_info = "false"
change_names_dont_change_bus_members = "false"
change_names_update_inst_tree = "true"
check_error_list = {"CMD-004", "CMD-006", "CMD-007", "CMD-008", "CMD-009", "CMD-010", "CMD-011", "CMD-012", "CMD-014", "CMD-015", "CMD-016", "CMD-019", "CMD-026", "CMD-031", "CMD-037", "DB-1", "DCSH-11", "DES-001", "FILE-1", "FILE-2", "FILE-3", "FILE-4", "LINK-5", "LINK-7", "LINT-7", "LINT-20", "LNK-023", "OPT-100", "OPT-101", "OPT-102", "OPT-114", "OPT-124", "OPT-127", "OPT-128", "OPT-155", "OPT-157", "OPT-181", "OPT-462", "UI-11", "UI-14", "UI-15", "UI-16", "UI-17", "UI-19", "UI-20", "UI-21", "UI-22", "UI-23", "UI-40", "UI-41", "UID-4", "UID-6", "UID-7", "UID-8", "UID-9", "UID-13", "UID-14", "UID-15", "UID-19", "UID-20", "UID-25", "UID-27", "UID-28", "UID-29", "UID-30", "UID-32", "UID-58", "UID-87", "UID-103", "UID-109", "UID-270", "UID-272", "UID-403", "UID-440", "UID-444", "UIO-2", "UIO-3", "UIO-4", "UIO-25", "UIO-65", "UIO-66", "UIO-75", "UIO-94", "UIO-95", "EQN-6", "EQN-11", "EQN-15", "EQN-16", "EQN-18", "EQN-20"}
command_log_file = "./command.log"
company = "OREGANO SYSTEMS"
compatibility_version = "1999.10"
compile_assume_fully_decoded_three_state_busses = "false"
compile_automatic_clock_phase_inference = "strict"
compile_checkpoint_cpu_interval = 0.000000
compile_checkpoint_filename = "./CHECKPOINT.db"
compile_checkpoint_phases = "false"
compile_checkpoint_pre_area_filename = "./CHECKPOINT_PRE_AREA.db"
compile_checkpoint_pre_delay_filename = "./CHECKPOINT_PRE_DELAY.db"
compile_checkpoint_pre_drc1_filename = "./CHECKPOINT_PRE_DRC1.db"
compile_checkpoint_pre_drc2_filename = "./CHECKPOINT_PRE_DRC2.db"
compile_cpu_limit = 0.000000
compile_create_mux_op_hierarchy = "true"
compile_create_wire_load_table = "false"
compile_delete_unloaded_sequential_cells = "true"
compile_disable_hierarchical_inverter_opt = "false"
compile_dont_touch_annotated_cell_during_inplace_opt = "false"
compile_dont_use_dedicated_scanout = 1
compile_dw_simple_mode = "false"
compile_fix_cell_degradation = "false"
compile_implementation_selection = "true"
compile_instance_name_prefix = "U"
compile_instance_name_suffix = ""
compile_log_format = "  %elap_time %area %wns %tns %drc %endpoint"
compile_mux_no_boundary_optimization = "false"
compile_negative_logic_methodology = "false"
compile_new_boolean_structure = "false"
compile_no_new_cells_at_top_level = "false"
compile_preserve_subdesign_interfaces = "false"
compile_sequential_area_recovery = "false"
compile_simple_mode_block_effort = "none"
compile_top_all_paths = "false"
compile_update_annotated_delays_during_inplace_opt = "true"
compile_use_fast_delay_mode = "true"
compile_use_low_timing_effort = "false"
context_check_status = "false"
create_clock_no_input_delay = "false"
current_design = "<<undefined>>"
current_instance = "<<undefined>>"
db2sge_bit_type = "std_logic"
db2sge_bit_vector_type = "std_logic_vector"
db2sge_command = "/home/synopsys.9910/sparcOS5/syn/bin/db2sge"
db2sge_display_instance_names = "false"
db2sge_display_pin_names = "false"
db2sge_display_symbol_names = "false"
db2sge_one_name = "'1'"
db2sge_output_directory = ""
db2sge_overwrite = "true"
db2sge_scale = 2
db2sge_script = "/home/synopsys.9910/admin/setup/.dc_write_sge"
db2sge_target_xp = "false"
db2sge_tcf_package_file = "synopsys_tcf.vhd"
db2sge_unknown_name = "'X'"
db2sge_use_bustaps = "false"
db2sge_use_compound_names = "true"
db2sge_use_lib_section = ""
db2sge_zero_name = "'0'"
dc_shell_mode = "default"
dc_shell_status = 1
default_input_delay = 30.000000
default_name_rules = ""
default_output_delay = 30.000000
default_port_connection_class = "universal"
default_schematic_options = "-size infinite"
design_library_file = ".synopsys_vss.setup"
designer = "Roland H鰈ler"
dpcm_debuglevel = "0"
dpcm_functionscope = "global"
dpcm_level = "performance"
dpcm_libraries = {}
dpcm_rulepath = {}
dpcm_rulespath = {}
dpcm_slewlimit = "TRUE"
dpcm_tablepath = {}
dpcm_temperaturescope = "global"
dpcm_version = "IEEE-P1481"
dpcm_voltagescope = "global"
dpcm_wireloadscope = "global"
duplicate_ports = "false"
echo_include_commands = "true"
eco_align_design_verbose = "false"
eco_allow_register_type_difference = "false"
eco_connect_resource_cell_inputs = "true"
eco_correspondence_analysis_verbose = "false"
eco_directives_verbose = "false"
eco_implement_effort_level = "low"
eco_instance_name_prefix = "eco_"
eco_recycle_verbose = "true"
eco_remap_register_verbose = "false"
eco_reuse_verbose = "false"
edifin_autoconnect_offpageconnectors = "false"
edifin_autoconnect_ports = "false"
edifin_dc_script_flag = ""
edifin_delete_empty_cells = "true"
edifin_delete_ripper_cells = "true"
edifin_ground_net_name = ""
edifin_ground_net_property_name = ""
edifin_ground_net_property_value = ""
edifin_ground_port_name = ""
edifin_instance_property_name = ""
edifin_lib_in_osc_symbol = ""
edifin_lib_in_port_symbol = ""
edifin_lib_inout_osc_symbol = ""
edifin_lib_inout_port_symbol = ""
edifin_lib_logic_0_symbol = ""
edifin_lib_logic_1_symbol = ""
edifin_lib_mentor_netcon_symbol = ""
edifin_lib_out_osc_symbol = ""
edifin_lib_out_port_symbol = ""
edifin_lib_ripper_bits_property = ""
edifin_lib_ripper_bus_end = ""
edifin_lib_ripper_cell_name = ""
edifin_lib_ripper_view_name = ""
edifin_lib_route_grid = 1024
edifin_lib_templates = {}
edifin_portinstance_disabled_property_name = ""
edifin_portinstance_disabled_property_value = ""
edifin_portinstance_property_name = ""
edifin_power_net_name = ""
edifin_power_net_property_name = ""
edifin_power_net_property_value = ""
edifin_power_port_name = ""
edifin_use_identifier_in_rename = "false"
edifin_view_identifier_property_name = ""
edifout_dc_script_flag = ""
edifout_design_name = "Synopsys_edif"
edifout_designs_library_name = "DESIGNS"
edifout_display_instance_names = "false"
edifout_display_net_names = "false"
edifout_external = "true"
edifout_external_graphic_view_name = "Graphic_representation"
edifout_external_netlist_view_name = "Netlist_representation"
edifout_external_schematic_view_name = "Schematic_representation"
edifout_ground_name = "logic_0"
edifout_ground_net_name = ""
edifout_ground_net_property_name = ""
edifout_ground_net_property_value = ""
edifout_ground_pin_name = "logic_0_pin"
edifout_ground_port_name = "GND"
edifout_instance_property_name = ""
edifout_instantiate_ports = "false"
edifout_library_graphic_view_name = "Graphic_representation"
edifout_library_netlist_view_name = "Netlist_representation"
edifout_library_schematic_view_name = "Schematic_representation"
edifout_merge_libraries = "false"
edifout_multidimension_arrays = "false"
edifout_name_oscs_different_from_ports = "false"
edifout_name_rippers_same_as_wires = "false"
edifout_netlist_only = "true"
edifout_no_array = "true"
edifout_numerical_array_members = "false"
edifout_pin_direction_in_value = ""
edifout_pin_direction_inout_value = ""
edifout_pin_direction_out_value = ""
edifout_pin_direction_property_name = ""
edifout_pin_name_property_name = ""
edifout_portinstance_disabled_property_name = ""
edifout_portinstance_disabled_property_value = ""
edifout_portinstance_property_name = ""
edifout_power_and_ground_representation = "cell"
edifout_power_name = "logic_1"
edifout_power_net_name = ""
edifout_power_net_property_name = ""
edifout_power_net_property_value = ""
edifout_power_pin_name = "logic_1_pin"
edifout_power_port_name = "VDD"
edifout_skip_port_implementations = "false"
edifout_target_system = ""
edifout_top_level_symbol = "true"
edifout_translate_origin = ""
edifout_unused_property_value = ""
edifout_write_attributes = "false"
edifout_write_constraints = "false"
edifout_write_properties_list = {"INIT", "IO", "LOC", "PWR_MODE", "PAD_LOCATION", "PART"}
enable_instances_in_report_net = "false"
enable_page_mode = "true"
enable_recovery_removal_arcs = "false"
equationout_and_sign = "*"
equationout_or_sign = "+"
equationout_postfix_negation = "true"
errorcode = "NONE"
estimate_resource_preference = "fast"
exit_delete_filename_log_file = "true"
filename_log_file = "filenames.log"
find_converts_name_lists = "false"
found_arch_apollo = 0
found_x11_vendor_string_apollo = 0
gen_bussing_exact_implicit = "false"
gen_cell_pin_name_separator = "/"
gen_create_netlist_busses = "true"
gen_dont_show_single_bit_busses = "false"
gen_match_ripper_wire_widths = "false"
gen_max_compound_name_length = 256
gen_max_ports_on_symbol_side = 0
gen_open_name_postfix = ""
gen_open_name_prefix = "Open"
gen_show_created_busses = "false"
gen_show_created_symbols = "false"
gen_single_osc_per_name = "false"
generic_symbol_library = "generic.sdb"
hdl_keep_licenses = "true"
hdl_naming_threshold = 20
hdl_preferred_license = ""
hdlin_advisor_directory = "."
hdlin_auto_save_templates = "FALSE"
hdlin_check_no_latch = "FALSE"
hdlin_dont_check_param_width = "FALSE"
hdlin_dont_infer_mux_for_resource_sharing = "true"
hdlin_dont_turbo_instances_with_generics = "true"
hdlin_enable_analysis_info = "false"
hdlin_enable_analysis_info_for_analyze = "true"
hdlin_enable_vpp = "false"
hdlin_ff_always_async_set_reset = "TRUE"
hdlin_ff_always_sync_set_reset = "FALSE"
hdlin_hide_resource_line_numbers = "FALSE"
hdlin_infer_multibit = "default_none"
hdlin_infer_mux = "default"
hdlin_keep_feedback = "FALSE"
hdlin_keep_inv_feedback = "TRUE"
hdlin_latch_always_async_set_reset = "FALSE"
hdlin_merge_nested_conditional_statements = "false"
hdlin_mux_oversize_ratio = 100
hdlin_mux_size_limit = 32
hdlin_preserve_vpp_files = "false"
hdlin_reg_report_length = 60
hdlin_replace_synthetic = "FALSE"
hdlin_report_inferred_modules = "true"
hdlin_translate_off_skip_text = "false"
hdlin_vhdl93_concat = "true"
hdlin_vpp_temporary_directory = ""
hdlin_write_gtech_design_directory = "."
hdlout_internal_busses = "FALSE"
hier_dont_trace_ungroup = 0
hlo_ignore_priorities = "false"
hlo_minimize_tree_delay = "true"
hlo_resource_allocation = "constraint_driven"
hlo_resource_implementation = "use_fastest"
hlo_share_common_subexpressions = "true"
hlo_share_effort = "low"
hlo_transform_constant_multiplication = "false"
init_path = "/home/synopsys.9910/auxx/syn"
insert_test_design_naming_style = "%s_test_%d"
jtag_manufacturer_id = 0
jtag_part_number = 65535
jtag_port_drive_limit = 6
jtag_test_clock_port_naming_style = "jtag_tck%s"
jtag_test_data_in_port_naming_style = "jtag_tdi%s"
jtag_test_data_out_port_naming_style = "jtag_tdo%s"
jtag_test_mode_select_port_naming_style = "jtag_tms%s"
jtag_test_reset_port_naming_style = "jtag_trst%s"
jtag_version_number = 0
lbo_cells_in_regions = "false"
ldd_return_val = "0"
ldd_script = "/home/synopsys.9910/auxx/syn/scripts/list_duplicate_designs.dcsh"
libgen_max_differences = -1
link_force_case = "check_reference"
link_library = {"*", "MTC45000.db", "MTC45000_WL_WORST.db"}
lsiin_net_name_prefix = "NET_"
lsiout_inverter_cell = ""
lsiout_upcase = "true"
ltl_drc_use_center_of_mass = "true"
ltl_enable_mean_physical_port_location = "false"
ltl_lbo_use_all_transforms = "true"
ltl_new_critical_net_fixing_delay = "true"
ltl_new_critical_net_fixing_drc = "true"
mentor_bidirect_value = "INOUT"
mentor_do_path = ""
mentor_input_output_property_name = "PINTYPE"
mentor_input_value = "IN"
mentor_logic_one_value = "1SF"
mentor_logic_zero_one_property_name = "INIT"
mentor_logic_zero_value = "0SF"
mentor_output_value = "OUT"
mentor_primitive_property_name = "PRIMITIVE"
mentor_primitive_property_value = "MODULE"
mentor_reference_property_name = "COMP"
mentor_search_path = ""
mentor_write_symbols = "true"