bcd.tan.qmsg

用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8位优先编码器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[12\] register cnt\[19\] 76.92 MHz 13.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 76.92 MHz between source register \"cnt\[12\]\" and destination register \"cnt\[19\]\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[12\] 1 REG LC113 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC113; Fanout = 13; REG Node = 'cnt\[12\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "" { cnt[12] } "NODE_NAME" } "" } } { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns cnt\[19\] 2 REG LC123 5 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC123; Fanout = 5; REG Node = 'cnt\[19\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "8.000 ns" { cnt[12] cnt[19] } "NODE_NAME" } "" } } { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "8.000 ns" { cnt[12] cnt[19] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { cnt[12] cnt[19] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 22 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 22; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "" { clk } "NODE_NAME" } "" } } { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns cnt\[19\] 2 REG LC123 5 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC123; Fanout = 5; REG Node = 'cnt\[19\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "0.000 ns" { clk cnt[19] } "NODE_NAME" } "" } } { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "3.000 ns" { clk cnt[19] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out cnt[19] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 22 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 22; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "" { clk } "NODE_NAME" } "" } } { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns cnt\[12\] 2 REG LC113 13 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC113; Fanout = 13; REG Node = 'cnt\[12\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "0.000 ns" { clk cnt[12] } "NODE_NAME" } "" } } { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "3.000 ns" { clk cnt[12] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out cnt[12] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "3.000 ns" { clk cnt[19] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out cnt[19] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "3.000 ns" { clk cnt[12] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out cnt[12] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 17 -1 0 } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "8.000 ns" { cnt[12] cnt[19] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { cnt[12] cnt[19] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "3.000 ns" { clk cnt[19] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out cnt[19] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "3.000 ns" { clk cnt[12] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out cnt[12] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk c\[2\] en\[1\]~reg0 27.000 ns register " "Info: tco from clock \"clk\" to destination pin \"c\[2\]\" through register \"en\[1\]~reg0\" is 27.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 22 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 22; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "" { clk } "NODE_NAME" } "" } } { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns en\[1\]~reg0 2 REG LC118 37 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC118; Fanout = 37; REG Node = 'en\[1\]~reg0'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "0.000 ns" { clk en[1]~reg0 } "NODE_NAME" } "" } } { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 31 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "3.000 ns" { clk en[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out en[1]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 31 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "23.000 ns + Longest register pin " "Info: + Longest register to pin delay is 23.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns en\[1\]~reg0 1 REG LC118 37 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC118; Fanout = 37; REG Node = 'en\[1\]~reg0'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "" { en[1]~reg0 } "NODE_NAME" } "" } } { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns reduce_or~1654 2 COMB LC100 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC100; Fanout = 1; COMB Node = 'reduce_or~1654'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "8.000 ns" { en[1]~reg0 reduce_or~1654 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 10.000 ns reduce_or~1624 3 COMB LC101 1 " "Info: 3: + IC(0.000 ns) + CELL(2.000 ns) = 10.000 ns; Loc. = LC101; Fanout = 1; COMB Node = 'reduce_or~1624'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "2.000 ns" { reduce_or~1654 reduce_or~1624 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 19.000 ns reduce_or~1656 4 COMB LC86 1 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC86; Fanout = 1; COMB Node = 'reduce_or~1656'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "9.000 ns" { reduce_or~1624 reduce_or~1656 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 23.000 ns c\[2\] 5 PIN PIN_56 0 " "Info: 5: + IC(0.000 ns) + CELL(4.000 ns) = 23.000 ns; Loc. = PIN_56; Fanout = 0; PIN Node = 'c\[2\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "4.000 ns" { reduce_or~1656 c[2] } "NODE_NAME" } "" } } { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "19.000 ns 82.61 % " "Info: Total cell delay = 19.000 ns ( 82.61 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 17.39 % " "Info: Total interconnect delay = 4.000 ns ( 17.39 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "23.000 ns" { en[1]~reg0 reduce_or~1654 reduce_or~1624 reduce_or~1656 c[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { en[1]~reg0 reduce_or~1654 reduce_or~1624 reduce_or~1656 c[2] } { 0.000ns 2.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 2.000ns 7.000ns 4.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "3.000 ns" { clk en[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out en[1]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "23.000 ns" { en[1]~reg0 reduce_or~1654 reduce_or~1624 reduce_or~1656 c[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { en[1]~reg0 reduce_or~1654 reduce_or~1624 reduce_or~1656 c[2] } { 0.000ns 2.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 2.000ns 7.000ns 4.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[0\] c\[2\] 25.000 ns Longest " "Info: Longest tpd from source pin \"a\[0\]\" to destination pin \"c\[2\]\" is 25.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns a\[0\] 1 PIN PIN_24 19 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_24; Fanout = 19; PIN Node = 'a\[0\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "" { a[0] } "NODE_NAME" } "" } } { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns reduce_or~1654 2 COMB LC100 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC100; Fanout = 1; COMB Node = 'reduce_or~1654'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "8.000 ns" { a[0] reduce_or~1654 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 12.000 ns reduce_or~1624 3 COMB LC101 1 " "Info: 3: + IC(0.000 ns) + CELL(2.000 ns) = 12.000 ns; Loc. = LC101; Fanout = 1; COMB Node = 'reduce_or~1624'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "2.000 ns" { reduce_or~1654 reduce_or~1624 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 21.000 ns reduce_or~1656 4 COMB LC86 1 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 21.000 ns; Loc. = LC86; Fanout = 1; COMB Node = 'reduce_or~1656'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "9.000 ns" { reduce_or~1624 reduce_or~1656 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 25.000 ns c\[2\] 5 PIN PIN_56 0 " "Info: 5: + IC(0.000 ns) + CELL(4.000 ns) = 25.000 ns; Loc. = PIN_56; Fanout = 0; PIN Node = 'c\[2\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "4.000 ns" { reduce_or~1656 c[2] } "NODE_NAME" } "" } } { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.000 ns 84.00 % " "Info: Total cell delay = 21.000 ns ( 84.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 16.00 % " "Info: Total interconnect delay = 4.000 ns ( 16.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd_cmp.qrpt" Compiler "bcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/" "" "25.000 ns" { a[0] reduce_or~1654 reduce_or~1624 reduce_or~1656 c[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "25.000 ns" { a[0] a[0]~out reduce_or~1654 reduce_or~1624 reduce_or~1656 c[2] } { 0.000ns 0.000ns 2.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 6.000ns 2.000ns 7.000ns 4.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 14 11:09:12 2005 " "Info: Processing ended: Wed Dec 14 11:09:12 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}