bcd.map.qmsg

用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8位优先编码器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 14 11:09:04 2005 " "Info: Processing started: Wed Dec 14 11:09:04 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off bcd -c bcd " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off bcd -c bcd" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bcd.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file bcd.v" { { "Info" "ISGN_ENTITY_NAME" "1 bcd " "Info: Found entity 1: bcd" {  } { { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "bcd " "Info: Elaborating entity \"bcd\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 bcd.v(22) " "Warning: Verilog HDL assignment warning at bcd.v(22): truncated value with size 32 to match size of target (20)" {  } { { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 22 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 bcd.v(24) " "Warning: Verilog HDL assignment warning at bcd.v(24): truncated value with size 32 to match size of target (20)" {  } { { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 24 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 bcd.v(26) " "Warning: Verilog HDL assignment warning at bcd.v(26): truncated value with size 32 to match size of target (20)" {  } { { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 26 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "code_data bcd.v(43) " "Warning: Verilog HDL Always Construct warning at bcd.v(43): variable \"code_data\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 43 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "code_data bcd.v(45) " "Warning: Verilog HDL Always Construct warning at bcd.v(45): variable \"code_data\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 45 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 bcd.v(47) " "Warning: Verilog HDL assignment warning at bcd.v(47): truncated value with size 32 to match size of target (4)" {  } { { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 47 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "bcd.v(41) " "Info: Verilog HDL Case Statement information at bcd.v(41): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement" {  } { { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 41 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "look_add.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "20 " "Info: Ignored 20 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "20 " "Info: Ignored 20 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 10 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "c\[0\] VCC " "Warning: Pin \"c\[0\]\" stuck at VCC" {  } { { "bcd.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/二进制转BCD码/bcd.v" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "rst " "Info: Promoted clear signal driven by pin \"rst\" to global clear signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "49 " "Info: Implemented 49 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "33 " "Info: Implemented 33 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 14 11:09:07 2005 " "Info: Processing ended: Wed Dec 14 11:09:07 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}