state_machine.smp_dump.txt

用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8位优先编码器

State Machine - |state_machine|state
Name state~48 state~47 state~46 
state.state0 0 0 0 
state.state6 1 1 0 
state.state5 1 0 1 
state.state4 1 0 0 
state.state3 0 1 1 
state.state2 0 1 0 
state.state1 0 0 1 
state.state7 1 1 1