sub.tan.qmsg

用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8位优先编码器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 12 10:24:41 2005 " "Info: Processing started: Wed Oct 12 10:24:41 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off sub -c sub " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sub -c sub" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b\[3\] c\[6\] 32.000 ns Longest " "Info: Longest tpd from source pin \"b\[3\]\" to destination pin \"c\[6\]\" is 32.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns b\[3\] 1 PIN PIN_15 160 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_15; Fanout = 160; PIN Node = 'b\[3\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/db/sub_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/db/sub_cmp.qrpt" Compiler "sub" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/db/sub.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/" "" "" { b[3] } "NODE_NAME" } "" } } { "sub.v" "" { Text "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/sub.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 12.000 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|sout_node\[4\]~37 2 COMB SEXP100 1 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP100; Fanout = 1; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|sout_node\[4\]~37'" {  } { { "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/db/sub_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/db/sub_cmp.qrpt" Compiler "sub" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/db/sub.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/" "" "10.000 ns" { b[3] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[4]~37 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 42 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 19.000 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|sout_node\[4\]~39 3 COMB LC101 7 " "Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC101; Fanout = 7; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|sout_node\[4\]~39'" {  } { { "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/db/sub_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/db/sub_cmp.qrpt" Compiler "sub" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/db/sub.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/" "" "7.000 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[4]~37 lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[4]~39 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 42 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 28.000 ns reduce_or~1260 4 COMB LC85 1 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 28.000 ns; Loc. = LC85; Fanout = 1; COMB Node = 'reduce_or~1260'" {  } { { "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/db/sub_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/db/sub_cmp.qrpt" Compiler "sub" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/db/sub.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/" "" "9.000 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[4]~39 reduce_or~1260 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 32.000 ns c\[6\] 5 PIN PIN_55 0 " "Info: 5: + IC(0.000 ns) + CELL(4.000 ns) = 32.000 ns; Loc. = PIN_55; Fanout = 0; PIN Node = 'c\[6\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/db/sub_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/db/sub_cmp.qrpt" Compiler "sub" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/db/sub.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/" "" "4.000 ns" { reduce_or~1260 c[6] } "NODE_NAME" } "" } } { "sub.v" "" { Text "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/sub.v" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "28.000 ns 87.50 % " "Info: Total cell delay = 28.000 ns ( 87.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 12.50 % " "Info: Total interconnect delay = 4.000 ns ( 12.50 % )" {  } {  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/db/sub_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/db/sub_cmp.qrpt" Compiler "sub" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/db/sub.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/减法器/" "" "32.000 ns" { b[3] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[4]~37 lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[4]~39 reduce_or~1260 c[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "32.000 ns" { b[3] b[3]~out lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[4]~37 lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[4]~39 reduce_or~1260 c[6] } { 0.000ns 0.000ns 2.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 7.000ns 7.000ns 4.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 12 10:24:42 2005 " "Info: Processing ended: Wed Oct 12 10:24:42 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}