add.tan.qmsg

用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8位优先编码器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 12 10:23:16 2005 " "Info: Processing started: Wed Oct 12 10:23:16 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off add -c add " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off add -c add" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[2\] c\[4\] 25.000 ns Longest " "Info: Longest tpd from source pin \"a\[2\]\" to destination pin \"c\[4\]\" is 25.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns a\[2\] 1 PIN PIN_21 66 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_21; Fanout = 66; PIN Node = 'a\[2\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/db/add_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/db/add.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/" "" "" { a[2] } "NODE_NAME" } "" } } { "add.v" "" { Text "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/add.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns reduce_or~2873 2 COMB LC100 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC100; Fanout = 1; COMB Node = 'reduce_or~2873'" {  } { { "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/db/add_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/db/add.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/" "" "8.000 ns" { a[2] reduce_or~2873 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 12.000 ns reduce_or~2831 3 COMB LC101 1 " "Info: 3: + IC(0.000 ns) + CELL(2.000 ns) = 12.000 ns; Loc. = LC101; Fanout = 1; COMB Node = 'reduce_or~2831'" {  } { { "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/db/add_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/db/add.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/" "" "2.000 ns" { reduce_or~2873 reduce_or~2831 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 21.000 ns reduce_or~2839 4 COMB LC93 1 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 21.000 ns; Loc. = LC93; Fanout = 1; COMB Node = 'reduce_or~2839'" {  } { { "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/db/add_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/db/add.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/" "" "9.000 ns" { reduce_or~2831 reduce_or~2839 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 25.000 ns c\[4\] 5 PIN PIN_60 0 " "Info: 5: + IC(0.000 ns) + CELL(4.000 ns) = 25.000 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'c\[4\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/db/add_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/db/add.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/" "" "4.000 ns" { reduce_or~2839 c[4] } "NODE_NAME" } "" } } { "add.v" "" { Text "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/add.v" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.000 ns 84.00 % " "Info: Total cell delay = 21.000 ns ( 84.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 16.00 % " "Info: Total interconnect delay = 4.000 ns ( 16.00 % )" {  } {  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/db/add_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/db/add.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/" "" "25.000 ns" { a[2] reduce_or~2873 reduce_or~2831 reduce_or~2839 c[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "25.000 ns" { a[2] a[2]~out reduce_or~2873 reduce_or~2831 reduce_or~2839 c[4] } { 0.000ns 0.000ns 2.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 6.000ns 2.000ns 7.000ns 4.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 12 10:23:17 2005 " "Info: Processing ended: Wed Oct 12 10:23:17 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}