add.map.qmsg

用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8位优先编码器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 12 10:22:53 2005 " "Info: Processing started: Wed Oct 12 10:22:53 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off add -c add " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off add -c add" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file add.v" { { "Info" "ISGN_ENTITY_NAME" "1 add " "Info: Found entity 1: add" {  } { { "add.v" "" { Text "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/add.v" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "add " "Info: Elaborating entity \"add\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 add.v(14) " "Warning: Verilog HDL assignment warning at add.v(14): truncated value with size 32 to match size of target (1)" {  } { { "add.v" "" { Text "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/add.v" 14 0 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "c\[0\] VCC " "Warning: Pin \"c\[0\]\" stuck at VCC" {  } { { "add.v" "" { Text "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/add.v" 8 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en GND " "Warning: Pin \"en\" stuck at GND" {  } { { "add.v" "" { Text "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/加法器/add.v" 10 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "42 " "Info: Implemented 42 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "21 " "Info: Implemented 21 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "6 " "Info: Implemented 6 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 12 10:23:02 2005 " "Info: Processing ended: Wed Oct 12 10:23:02 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0}  } {  } 0}