mlt.qws

来自「用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8」· QWS 代码 · 共 20 行

[ProjectWorkspace]
ptn_Child1=Frames
ptn_Child2=ActionPoints
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
ptn_Child3=Document-2
[ProjectWorkspace.Frames.ChildFrames.Document-0]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
DocPathName=mlt.v
DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde}
WindowPlacement=MCAAAAAACAAAAAAADAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPEOPPPPPPBFAAAAAABFAAAAAAEPCAAAAACJBAAAAA
IsActiveChildFrame=True
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0.StateMap]
AFC_IN_REPORT=False