mlt.tan.qmsg

用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8位优先编码器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 12 10:15:46 2005 " "Info: Processing started: Wed Oct 12 10:15:46 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off mlt -c mlt " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mlt -c mlt" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b\[0\] c\[4\] 15.000 ns Longest " "Info: Longest tpd from source pin \"b\[0\]\" to destination pin \"c\[4\]\" is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns b\[0\] 1 PIN PIN_21 14 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_21; Fanout = 14; PIN Node = 'b\[0\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/乘法器/db/mlt_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/乘法器/db/mlt_cmp.qrpt" Compiler "mlt" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/乘法器/db/mlt.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/乘法器/" "" "" { b[0] } "NODE_NAME" } "" } } { "mlt.v" "" { Text "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/乘法器/mlt.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 11.000 ns reduce_or~1057 2 COMB LC93 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC93; Fanout = 1; COMB Node = 'reduce_or~1057'" {  } { { "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/乘法器/db/mlt_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/乘法器/db/mlt_cmp.qrpt" Compiler "mlt" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/乘法器/db/mlt.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/乘法器/" "" "9.000 ns" { b[0] reduce_or~1057 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 15.000 ns c\[4\] 3 PIN PIN_60 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'c\[4\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/乘法器/db/mlt_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/乘法器/db/mlt_cmp.qrpt" Compiler "mlt" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/乘法器/db/mlt.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/乘法器/" "" "4.000 ns" { reduce_or~1057 c[4] } "NODE_NAME" } "" } } { "mlt.v" "" { Text "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/乘法器/mlt.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.000 ns 86.67 % " "Info: Total cell delay = 13.000 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 13.33 % " "Info: Total interconnect delay = 2.000 ns ( 13.33 % )" {  } {  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/乘法器/db/mlt_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/乘法器/db/mlt_cmp.qrpt" Compiler "mlt" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/乘法器/db/mlt.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盘/示例程序/Verilog/基础实验/乘法器/" "" "15.000 ns" { b[0] reduce_or~1057 c[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "15.000 ns" { b[0] b[0]~out reduce_or~1057 c[4] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 7.000ns 4.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 12 10:15:47 2005 " "Info: Processing ended: Wed Oct 12 10:15:47 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}