cmp.map.eqn

用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8位优先编码器

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L1 is LessThan~424
A1L1_p0_out = b[3] & !a[2] & b[2];
A1L1_p1_out = !a[3] & b[3];
A1L1_p2_out = !a[3] & !a[2] & b[2];
A1L1_p3_out = !a[3] & !a[2] & !a[1] & b[1];
A1L1_p4_out = !a[3] & !a[2] & !a[1] & !a[0] & b[0];
A1L1_or_out = A1L7 # A1L1_p0_out # A1L1_p1_out # A1L1_p2_out # A1L1_p3_out # A1L1_p4_out;
A1L1 = !(A1L1_or_out);


--A1L2 is LessThan~433
A1L2_p0_out = b[3] & !a[2] & b[2];
A1L2_p1_out = !a[3] & b[3];
A1L2_p2_out = !a[3] & !a[2] & b[2];
A1L2_p3_out = !a[3] & !a[2] & !a[1] & b[1];
A1L2_p4_out = !a[3] & !a[2] & !a[1] & !a[0] & b[0];
A1L2_or_out = A1L11 # A1L2_p0_out # A1L2_p1_out # A1L2_p2_out # A1L2_p3_out # A1L2_p4_out;
A1L2 = !(A1L2_or_out);


--A1L3 is LessThan~440
A1L3_p0_out = !a[0] & b[0] & b[2] & b[3] & b[1];
A1L3_p1_out = !a[1] & !a[0] & b[0] & b[2] & b[3];
A1L3_p2_out = !a[0] & b[0] & !a[2] & !a[3] & b[1];
A1L3_p3_out = !a[0] & b[0] & b[3] & !a[2] & b[1];
A1L3_p4_out = !a[0] & b[0] & b[2] & !a[3] & b[1];
A1L3_or_out = A1L6 # A1L3_p0_out # A1L3_p1_out # A1L3_p2_out # A1L3_p3_out # A1L3_p4_out;
A1L3 = !(A1L3_or_out);


--A1L4 is LessThan~449
A1L4_p0_out = b[3] & !a[2] & b[2];
A1L4_p1_out = !a[3] & b[3];
A1L4_p2_out = !a[3] & !a[2] & b[2];
A1L4_p3_out = !a[3] & !a[2] & !a[1] & b[1];
A1L4_p4_out = !a[3] & !a[2] & !a[1] & !a[0] & b[0];
A1L4_or_out = A1L9 # A1L4_p0_out # A1L4_p1_out # A1L4_p2_out # A1L4_p3_out # A1L4_p4_out;
A1L4 = !(A1L4_or_out);


--A1L5 is LessThan~451
A1L5_p0_out = b[3] & !a[2] & !a[1] & b[1];
A1L5_p1_out = !a[3] & b[3];
A1L5_p2_out = !a[3] & !a[2] & b[2];
A1L5_p3_out = b[3] & !a[2] & b[2];
A1L5_p4_out = !a[3] & !a[2] & !a[1] & b[1];
A1L5 = A1L5_p0_out # A1L5_p1_out # A1L5_p2_out # A1L5_p3_out # A1L5_p4_out;


--A1L6 is LessThan~457
A1L6_p0_out = !a[1] & !a[3] & b[2] & !a[0] & b[0];
A1L6_p1_out = !a[1] & !a[3] & b[1] & b[2];
A1L6_p2_out = !a[1] & b[1] & b[2] & b[3];
A1L6_p3_out = !a[1] & !a[3] & !a[2] & !a[0] & b[0];
A1L6_p4_out = !a[1] & b[3] & !a[2] & !a[0] & b[0];
A1L6 = A1L5 # A1L6_p0_out # A1L6_p1_out # A1L6_p2_out # A1L6_p3_out # A1L6_p4_out;


--~VCC~0 is ~VCC~0
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--~VCC~1 is ~VCC~1
~VCC~1_or_out = GND;
~VCC~1 = !(~VCC~1_or_out);


--~GND~0 is ~GND~0
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;


--~GND~1 is ~GND~1
~GND~1_or_out = GND;
~GND~1 = ~GND~1_or_out;


--~GND~2 is ~GND~2
~GND~2_or_out = GND;
~GND~2 = ~GND~2_or_out;


--~GND~3 is ~GND~3
~GND~3_or_out = GND;
~GND~3 = ~GND~3_or_out;


--~GND~4 is ~GND~4
~GND~4_or_out = GND;
~GND~4 = ~GND~4_or_out;


--~GND~5 is ~GND~5
~GND~5_or_out = GND;
~GND~5 = ~GND~5_or_out;


--~GND~6 is ~GND~6
~GND~6_or_out = GND;
~GND~6 = ~GND~6_or_out;


--~GND~7 is ~GND~7
~GND~7_or_out = GND;
~GND~7 = ~GND~7_or_out;


--~GND~8 is ~GND~8
~GND~8_or_out = GND;
~GND~8 = ~GND~8_or_out;


--~GND~9 is ~GND~9
~GND~9_or_out = GND;
~GND~9 = ~GND~9_or_out;


--A1L7 is LessThan~466
A1L7_p0_out = b[3] & !a[2] & b[1] & !a[0] & b[0];
A1L7_p1_out = b[3] & !a[2] & !a[1] & b[1];
A1L7_p2_out = b[3] & !a[2] & !a[1] & !a[0] & b[0];
A1L7_p3_out = b[3] & !a[1] & b[1] & b[2];
A1L7_p4_out = b[3] & !a[1] & !a[0] & b[0] & b[2];
A1L7 = A1L8 # A1L7_p0_out # A1L7_p1_out # A1L7_p2_out # A1L7_p3_out # A1L7_p4_out;


--A1L8 is LessThan~471
A1L8_p0_out = b[1] & !a[0] & b[0] & !a[3] & !a[2];
A1L8_p1_out = b[1] & b[2] & b[3] & !a[0] & b[0];
A1L8_p2_out = b[1] & b[2] & !a[3] & !a[1];
A1L8_p3_out = b[2] & !a[0] & b[0] & !a[3] & !a[1];
A1L8_p4_out = b[1] & b[2] & !a[0] & b[0] & !a[3];
A1L8 = A1L8_p0_out # A1L8_p1_out # A1L8_p2_out # A1L8_p3_out # A1L8_p4_out;


--A1L9 is LessThan~479
A1L9_p0_out = b[3] & !a[2] & b[1] & !a[0] & b[0];
A1L9_p1_out = b[3] & !a[2] & !a[1] & b[1];
A1L9_p2_out = b[3] & !a[2] & !a[1] & !a[0] & b[0];
A1L9_p3_out = b[3] & !a[1] & b[1] & b[2];
A1L9_p4_out = b[3] & !a[1] & !a[0] & b[0] & b[2];
A1L9 = A1L01 # A1L9_p0_out # A1L9_p1_out # A1L9_p2_out # A1L9_p3_out # A1L9_p4_out;


--A1L01 is LessThan~484
A1L01_p0_out = b[1] & !a[0] & b[0] & !a[3] & !a[2];
A1L01_p1_out = b[1] & b[2] & b[3] & !a[0] & b[0];
A1L01_p2_out = b[1] & b[2] & !a[3] & !a[1];
A1L01_p3_out = b[2] & !a[0] & b[0] & !a[3] & !a[1];
A1L01_p4_out = b[1] & b[2] & !a[0] & b[0] & !a[3];
A1L01 = A1L01_p0_out # A1L01_p1_out # A1L01_p2_out # A1L01_p3_out # A1L01_p4_out;


--A1L11 is LessThan~492
A1L11_p0_out = b[3] & !a[2] & b[1] & !a[0] & b[0];
A1L11_p1_out = b[3] & !a[2] & !a[1] & b[1];
A1L11_p2_out = b[3] & !a[2] & !a[1] & !a[0] & b[0];
A1L11_p3_out = b[3] & !a[1] & b[1] & b[2];
A1L11_p4_out = b[3] & !a[1] & !a[0] & b[0] & b[2];
A1L11 = A1L21 # A1L11_p0_out # A1L11_p1_out # A1L11_p2_out # A1L11_p3_out # A1L11_p4_out;


--A1L21 is LessThan~497
A1L21_p0_out = b[1] & !a[0] & b[0] & !a[3] & !a[2];
A1L21_p1_out = b[1] & b[2] & b[3] & !a[0] & b[0];
A1L21_p2_out = b[1] & b[2] & !a[3] & !a[1];
A1L21_p3_out = b[2] & !a[0] & b[0] & !a[3] & !a[1];
A1L21_p4_out = b[1] & b[2] & !a[0] & b[0] & !a[3];
A1L21 = A1L21_p0_out # A1L21_p1_out # A1L21_p2_out # A1L21_p3_out # A1L21_p4_out;


--a[0] is a[0]
--operation mode is input

a[0] = INPUT();


--a[1] is a[1]
--operation mode is input

a[1] = INPUT();


--a[2] is a[2]
--operation mode is input

a[2] = INPUT();


--a[3] is a[3]
--operation mode is input

a[3] = INPUT();


--b[0] is b[0]
--operation mode is input

b[0] = INPUT();


--b[1] is b[1]
--operation mode is input

b[1] = INPUT();


--b[2] is b[2]
--operation mode is input

b[2] = INPUT();


--b[3] is b[3]
--operation mode is input

b[3] = INPUT();


--c[0] is c[0]
--operation mode is output

c[0] = OUTPUT(~VCC~0);


--c[1] is c[1]
--operation mode is output

c[1] = OUTPUT(~VCC~1);


--c[5] is c[5]
--operation mode is output

c[5] = OUTPUT(~GND~0);


--c[6] is c[6]
--operation mode is output

c[6] = OUTPUT(~GND~1);


--en[0] is en[0]
--operation mode is output

en[0] = OUTPUT(~GND~2);


--en[1] is en[1]
--operation mode is output

en[1] = OUTPUT(~GND~3);


--en[2] is en[2]
--operation mode is output

en[2] = OUTPUT(~GND~4);


--en[3] is en[3]
--operation mode is output

en[3] = OUTPUT(~GND~5);


--en[4] is en[4]
--operation mode is output

en[4] = OUTPUT(~GND~6);


--en[5] is en[5]
--operation mode is output

en[5] = OUTPUT(~GND~7);


--en[6] is en[6]
--operation mode is output

en[6] = OUTPUT(~GND~8);


--en[7] is en[7]
--operation mode is output

en[7] = OUTPUT(~GND~9);


--c[7] is c[7]
--operation mode is output

c[7] = OUTPUT(A1L1);


--c[2] is c[2]
--operation mode is output

c[2] = OUTPUT(A1L4);


--c[3] is c[3]
--operation mode is output

c[3] = OUTPUT(A1L3);


--c[4] is c[4]
--operation mode is output

c[4] = OUTPUT(A1L2);