cmp.hier_info

用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8位优先编码器

|cmp
a[0] => LessThan~0.IN4
a[1] => LessThan~0.IN3
a[2] => LessThan~0.IN2
a[3] => LessThan~0.IN1
b[0] => LessThan~0.IN8
b[1] => LessThan~0.IN7
b[2] => LessThan~0.IN6
b[3] => LessThan~0.IN5
c[0] <= <VCC>
c[1] <= c~6.DB_MAX_OUTPUT_PORT_TYPE
c[2] <= c~5.DB_MAX_OUTPUT_PORT_TYPE
c[3] <= c~4.DB_MAX_OUTPUT_PORT_TYPE
c[4] <= c~3.DB_MAX_OUTPUT_PORT_TYPE
c[5] <= c~2.DB_MAX_OUTPUT_PORT_TYPE
c[6] <= c~1.DB_MAX_OUTPUT_PORT_TYPE
c[7] <= c~0.DB_MAX_OUTPUT_PORT_TYPE
en[0] <= <GND>
en[1] <= <GND>
en[2] <= <GND>
en[3] <= <GND>
en[4] <= <GND>
en[5] <= <GND>
en[6] <= <GND>
en[7] <= <GND>