traffic.v.bak

用verlog语言编的又一个很好的综合实验(交通灯的控制),特别适合于FPGA/CPLD的初学者

/*
本实验模拟路口的红黄绿交通灯的变化过程，用LED灯表示交通灯，并在数码管上显示当前状态剩余时间。
红灯持续时间为30秒，黄灯10秒，绿灯30秒
*/

module traffic(clk,rst,dataout,en,en1,light,light1);

input clk,rst;
output[7:0] dataout;//数码管段数据
reg[7:0] dataout;
output[1:0] en;     //数码管使能
output[2:0] light;  //红，黄，绿灯
reg[1:0] en;
reg[2:0] light;
output[8:0] light1;
output[5:0] en1;

reg[25:0] cnt;
reg[15:0] cnt_scan;
reg[3:0] dataout_buf;
reg[3:0] first,second;//时间的个位和十位
reg[1:0] state;

parameter red=2'b00,
		  yellow=2'b01,
		  green=2'b10;

assign light1=9'b111111111;
assign en1=6'b111111;

always@(posedge clk) 
begin
	if(!rst)
		cnt<=0;
	else if(cnt!=26'd40000000)
		cnt<=cnt+1;
	else
		cnt<=0;
end

always@(posedge clk)
begin
	if(!rst) begin
		state<=red;
		first<=0;
		second<=3;
	 end
	else begin
		if(cnt==24'd40000000) begin
			case(state)
				red: begin
					if(first!=0) 
						first<=first-1;
					else begin
						if(second!=0) begin
							second<=second-1;
							first<=9;
						 end
						else begin
							state<=green;
							second<=3;
						 end
					 end
				 end
				green: begin
					if(first!=0)
						first<=first-1;
					else begin
						if(second!=0) begin
							first<=9;
							second<=second-1;
						 end
						else begin
							state<=yellow;
							second<=1;
						 end
					 end
				 end
				yellow:begin
					if(first!=0||second!=0) begin
						if(second!=0) begin
							first<=9;
							second<=second-1;
						 end
						else
							first<=first-1;
					 end	 
					else begin
						state<=red;
						second<=3;
					 end
				 end
				default: begin
					first<=0;
					second<=0;
				 end
			 endcase
		 end
	 end
end

always@(state)
begin
	case(state)
		red: 
			light=3'b011;
		yellow:
			light=3'b101;
		green:
			light=3'b110;
		default:
			light=3'b111;
	 endcase
end

always@(posedge clk)
begin
	if(!rst) begin
		en<=2'b10;
		cnt_scan<=0;
	 end
	else begin
		cnt_scan<=cnt_scan+1;
		if(cnt_scan==16'hffff) 
			en<=~en;
	 end
end

always@(en or first or second)
begin
	case(en)
		2'b10:
			dataout_buf=first;
		2'b01:
			dataout_buf=second;
		default:
			dataout_buf=second;
	 endcase
end

always@(dataout_buf)
begin
	case(dataout_buf)
		4'b0000:
			dataout=8'b0000_0011;
		4'b0001:
			dataout=8'b1001_1111;
		4'b0010:
			dataout=8'b0010_0101;
		4'b0011:
			dataout=8'b0000_1101;
		4'b0100:
			dataout=8'b1001_1001;
		4'b0101:
			dataout=8'b0100_1001;
		4'b0110:
			dataout=8'b0100_0001;
		4'b0111:
			dataout=8'b0001_1111;
		4'b1000:
			dataout=8'b0000_0001;
		4'b1001:
			dataout=8'b0001_1001;
		4'b1010:
			dataout=8'b0001_0001;
		4'b1011:
			dataout=8'b1100_0001;
		4'b1100:
			dataout=8'b0110_0011;
		4'b1101:
			dataout=8'b1000_0101;
		4'b1110:
			dataout=8'b0110_0001;
		4'b1111:
			dataout=8'b0111_0001;
	 endcase
end

endmodule