traffic.map.rpt

用verlog语言编的又一个很好的综合实验(交通灯的控制),特别适合于FPGA/CPLD的初学者

; State Machine - |traffic|state     ;
+--------------+----------+----------+
; Name         ; state~48 ; state~47 ;
+--------------+----------+----------+
; state.red    ; 0        ; 0        ;
; state.green  ; 1        ; 0        ;
; state.yellow ; 0        ; 1        ;
+--------------+----------+----------+


+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |traffic ;
+----------------+-------+------------------------------------------------+
; Parameter Name ; Value ; Type                                           ;
+----------------+-------+------------------------------------------------+
; red            ; 00    ; Binary                                         ;
; yellow         ; 01    ; Binary                                         ;
; green          ; 10    ; Binary                                         ;
+----------------+-------+------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:cnt_scan_rtl_0 ;
+------------------------+----------+-----------------------------------------+
; Parameter Name         ; Value    ; Type                                    ;
+------------------------+----------+-----------------------------------------+
; AUTO_CARRY_CHAINS      ; ON       ; AUTO_CARRY                              ;
; IGNORE_CARRY_BUFFERS   ; OFF      ; IGNORE_CARRY                            ;
; AUTO_CASCADE_CHAINS    ; ON       ; AUTO_CASCADE                            ;
; IGNORE_CASCADE_BUFFERS ; OFF      ; IGNORE_CASCADE                          ;
; LPM_WIDTH              ; 16       ; Untyped                                 ;
; LPM_DIRECTION          ; UP       ; Untyped                                 ;
; LPM_MODULUS            ; 0        ; Untyped                                 ;
; LPM_AVALUE             ; UNUSED   ; Untyped                                 ;
; LPM_SVALUE             ; UNUSED   ; Untyped                                 ;
; DEVICE_FAMILY          ; MAX7000S ; Untyped                                 ;
; CARRY_CHAIN            ; MANUAL   ; Untyped                                 ;
; CARRY_CHAIN_LENGTH     ; 48       ; CARRY_CHAIN_LENGTH                      ;
; NOT_GATE_PUSH_BACK     ; ON       ; NOT_GATE_PUSH_BACK                      ;
; CARRY_CNT_EN           ; SMART    ; Untyped                                 ;
; LABWIDE_SCLR           ; ON       ; Untyped                                 ;
; USE_NEW_VERSION        ; TRUE     ; Untyped                                 ;
; CBXI_PARAMETER         ; NOTHING  ; Untyped                                 ;
+------------------------+----------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_1 ;
+------------------------+-------------+---------------------------------+
; Parameter Name         ; Value       ; Type                            ;
+------------------------+-------------+---------------------------------+
; LPM_WIDTH              ; 26          ; Untyped                         ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                         ;
; LPM_DIRECTION          ; ADD         ; Untyped                         ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                         ;
; LPM_PIPELINE           ; 0           ; Untyped                         ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                         ;
; REGISTERED_AT_END      ; 0           ; Untyped                         ;
; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                         ;
; USE_CS_BUFFERS         ; 1           ; Untyped                         ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                         ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH              ;
; DEVICE_FAMILY          ; MAX7000S    ; Untyped                         ;
; USE_WYS                ; OFF         ; Untyped                         ;
; STYLE                  ; FAST        ; Untyped                         ;
; CBXI_PARAMETER         ; add_sub_bph ; Untyped                         ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                  ;
+------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/交通灯/traffic.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Dec 14 14:42:43 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off traffic -c traffic
Warning: (10229) Verilog HDL Expression warning at traffic.v(45): truncated literal to match 24 bits
Info: Found 1 design units, including 1 entities, in source file traffic.v
    Info: Found entity 1: traffic
Info: Elaborating entity "traffic" for the top level hierarchy
Warning: Verilog HDL assignment warning at traffic.v(30): truncated value with size 32 to match size of target (26)
Warning: Verilog HDL assignment warning at traffic.v(32): truncated value with size 32 to match size of target (26)
Warning: Verilog HDL assignment warning at traffic.v(34): truncated value with size 32 to match size of target (26)
Warning: Verilog HDL assignment warning at traffic.v(41): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(42): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(49): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(52): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(53): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(57): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(63): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(66): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(67): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(71): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(78): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(79): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(82): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(86): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(90): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(91): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(118): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at traffic.v(121): truncated value with size 32 to match size of target (16)
Info: Verilog HDL Case Statement information at traffic.v(129): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: "cnt_scan[0]~0"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: State machine "|traffic|state" contains 3 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|traffic|state"
Info: Encoding result for state machine "|traffic|state"
    Info: Completed encoding using 2 state bits
        Info: Encoded state bit "state~48"
        Info: Encoded state bit "state~47"
    Info: State "|traffic|state.red" uses code string "00"
    Info: State "|traffic|state.green" uses code string "10"
    Info: State "|traffic|state.yellow" uses code string "01"
Info: Ignored 26 buffer(s)
    Info: Ignored 26 SOFT buffer(s)
Info: Registers with preset signals will power-up high
Warning: Reduced register "second[3]" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "dataout[0]" stuck at VCC
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
    Info: Promoted clear signal driven by pin "rst" to global clear signal
Info: Implemented 90 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 13 output pins
    Info: Implemented 74 macrocells
    Info: Implemented 1 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 25 warnings
    Info: Processing ended: Wed Dec 14 14:42:50 2005
    Info: Elapsed time: 00:00:07