clock.tan.qmsg

用verlog语言编的一个很好的综合实验,特别适合于FPGA/CPLD的初学者

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 6 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[19\] register cnt\[9\] 45.45 MHz 22.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 45.45 MHz between source register \"cnt\[19\]\" and destination register \"cnt\[9\]\" (period= 22.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.000 ns + Longest register register " "Info: + Longest register to register delay is 17.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[19\] 1 REG LC6 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6; Fanout = 19; REG Node = 'cnt\[19\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "" { cnt[19] } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns reduce_nor~989 2 COMB LC14 30 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC14; Fanout = 30; COMB Node = 'reduce_nor~989'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "9.000 ns" { cnt[19] reduce_nor~989 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 17.000 ns cnt\[9\] 3 REG LC40 30 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 17.000 ns; Loc. = LC40; Fanout = 30; REG Node = 'cnt\[9\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "8.000 ns" { reduce_nor~989 cnt[9] } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.000 ns 76.47 % " "Info: Total cell delay = 13.000 ns ( 76.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 23.53 % " "Info: Total interconnect delay = 4.000 ns ( 23.53 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "17.000 ns" { cnt[19] reduce_nor~989 cnt[9] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "17.000 ns" { cnt[19] reduce_nor~989 cnt[9] } { 0.000ns 2.000ns 2.000ns } { 0.000ns 7.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 74 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 74; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "" { clk } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns cnt\[9\] 2 REG LC40 30 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC40; Fanout = 30; REG Node = 'cnt\[9\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "0.000 ns" { clk cnt[9] } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "3.000 ns" { clk cnt[9] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out cnt[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 74 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 74; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "" { clk } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns cnt\[19\] 2 REG LC6 19 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC6; Fanout = 19; REG Node = 'cnt\[19\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "0.000 ns" { clk cnt[19] } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "3.000 ns" { clk cnt[19] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out cnt[19] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "3.000 ns" { clk cnt[9] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out cnt[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "3.000 ns" { clk cnt[19] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out cnt[19] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 13 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 13 -1 0 } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "17.000 ns" { cnt[19] reduce_nor~989 cnt[9] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "17.000 ns" { cnt[19] reduce_nor~989 cnt[9] } { 0.000ns 2.000ns 2.000ns } { 0.000ns 7.000ns 6.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "3.000 ns" { clk cnt[9] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out cnt[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "3.000 ns" { clk cnt[19] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out cnt[19] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[5\] en\[0\]~reg0 34.000 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[5\]\" through register \"en\[0\]~reg0\" is 34.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 74 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 74; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "" { clk } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns en\[0\]~reg0 2 REG LC118 36 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC118; Fanout = 36; REG Node = 'en\[0\]~reg0'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "0.000 ns" { clk en[0]~reg0 } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "3.000 ns" { clk en[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out en[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 27 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "30.000 ns + Longest register pin " "Info: + Longest register to pin delay is 30.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns en\[0\]~reg0 1 REG LC118 36 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC118; Fanout = 36; REG Node = 'en\[0\]~reg0'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "" { en[0]~reg0 } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 10.000 ns dataout_code\[0\]~606 2 COMB SEXP55 3 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 10.000 ns; Loc. = SEXP55; Fanout = 3; COMB Node = 'dataout_code\[0\]~606'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "10.000 ns" { en[0]~reg0 dataout_code[0]~606 } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 17.000 ns dataout_code\[2\]~636 3 COMB LC51 24 " "Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 17.000 ns; Loc. = LC51; Fanout = 24; COMB Node = 'dataout_code\[2\]~636'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "7.000 ns" { dataout_code[0]~606 dataout_code[2]~636 } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 26.000 ns reduce_or~1032 4 COMB LC97 1 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 26.000 ns; Loc. = LC97; Fanout = 1; COMB Node = 'reduce_or~1032'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "9.000 ns" { dataout_code[2]~636 reduce_or~1032 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 30.000 ns dataout\[5\] 5 PIN PIN_63 0 " "Info: 5: + IC(0.000 ns) + CELL(4.000 ns) = 30.000 ns; Loc. = PIN_63; Fanout = 0; PIN Node = 'dataout\[5\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "4.000 ns" { reduce_or~1032 dataout[5] } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "26.000 ns 86.67 % " "Info: Total cell delay = 26.000 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 13.33 % " "Info: Total interconnect delay = 4.000 ns ( 13.33 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "30.000 ns" { en[0]~reg0 dataout_code[0]~606 dataout_code[2]~636 reduce_or~1032 dataout[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "30.000 ns" { en[0]~reg0 dataout_code[0]~606 dataout_code[2]~636 reduce_or~1032 dataout[5] } { 0.000ns 2.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 8.000ns 7.000ns 7.000ns 4.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "3.000 ns" { clk en[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out en[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/" "" "30.000 ns" { en[0]~reg0 dataout_code[0]~606 dataout_code[2]~636 reduce_or~1032 dataout[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "30.000 ns" { en[0]~reg0 dataout_code[0]~606 dataout_code[2]~636 reduce_or~1032 dataout[5] } { 0.000ns 2.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 8.000ns 7.000ns 7.000ns 4.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 14 14:45:28 2005 " "Info: Processing ended: Wed Dec 14 14:45:28 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}