clock.map.rpt

用verlog语言编的一个很好的综合实验,特别适合于FPGA/CPLD的初学者

+-----------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                     ;
+---------------------------------+------------+------+-----------------------------------+
; Compilation Hierarchy Node      ; Macrocells ; Pins ; Full Hierarchy Name               ;
+---------------------------------+------------+------+-----------------------------------+
; |clock                          ; 95         ; 18   ; |clock                            ;
;    |lpm_counter:cnt_scan_rtl_0| ; 16         ; 0    ; |clock|lpm_counter:cnt_scan_rtl_0 ;
+---------------------------------+------------+------+-----------------------------------+


+-----------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:cnt_scan_rtl_0 ;
+------------------------+----------+-----------------------------------------+
; Parameter Name         ; Value    ; Type                                    ;
+------------------------+----------+-----------------------------------------+
; AUTO_CARRY_CHAINS      ; ON       ; AUTO_CARRY                              ;
; IGNORE_CARRY_BUFFERS   ; OFF      ; IGNORE_CARRY                            ;
; AUTO_CASCADE_CHAINS    ; ON       ; AUTO_CASCADE                            ;
; IGNORE_CASCADE_BUFFERS ; OFF      ; IGNORE_CASCADE                          ;
; LPM_WIDTH              ; 16       ; Untyped                                 ;
; LPM_DIRECTION          ; UP       ; Untyped                                 ;
; LPM_MODULUS            ; 0        ; Untyped                                 ;
; LPM_AVALUE             ; UNUSED   ; Untyped                                 ;
; LPM_SVALUE             ; UNUSED   ; Untyped                                 ;
; DEVICE_FAMILY          ; MAX7000S ; Untyped                                 ;
; CARRY_CHAIN            ; MANUAL   ; Untyped                                 ;
; CARRY_CHAIN_LENGTH     ; 48       ; CARRY_CHAIN_LENGTH                      ;
; NOT_GATE_PUSH_BACK     ; ON       ; NOT_GATE_PUSH_BACK                      ;
; CARRY_CNT_EN           ; SMART    ; Untyped                                 ;
; LABWIDE_SCLR           ; ON       ; Untyped                                 ;
; USE_NEW_VERSION        ; TRUE     ; Untyped                                 ;
; CBXI_PARAMETER         ; NOTHING  ; Untyped                                 ;
+------------------------+----------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_1 ;
+------------------------+-------------+---------------------------------+
; Parameter Name         ; Value       ; Type                            ;
+------------------------+-------------+---------------------------------+
; LPM_WIDTH              ; 26          ; Untyped                         ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                         ;
; LPM_DIRECTION          ; ADD         ; Untyped                         ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                         ;
; LPM_PIPELINE           ; 0           ; Untyped                         ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                         ;
; REGISTERED_AT_END      ; 0           ; Untyped                         ;
; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                         ;
; USE_CS_BUFFERS         ; 1           ; Untyped                         ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                         ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH              ;
; DEVICE_FAMILY          ; MAX7000S    ; Untyped                         ;
; USE_WYS                ; OFF         ; Untyped                         ;
; STYLE                  ; FAST        ; Untyped                         ;
; CBXI_PARAMETER         ; add_sub_bph ; Untyped                         ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                  ;
+------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Dec 14 14:45:09 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock
Info: Found 1 design units, including 1 entities, in source file clock.v
    Info: Found entity 1: clock
Info: Elaborating entity "clock" for the top level hierarchy
Warning: Verilog HDL assignment warning at clock.v(18): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clock.v(19): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clock.v(20): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clock.v(21): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clock.v(22): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clock.v(23): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clock.v(28): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at clock.v(32): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at clock.v(67): truncated value with size 32 to match size of target (26)
Warning: Verilog HDL assignment warning at clock.v(69): truncated value with size 32 to match size of target (26)
Warning: Verilog HDL assignment warning at clock.v(71): truncated value with size 32 to match size of target (26)
Warning: Verilog HDL assignment warning at clock.v(77): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(78): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(79): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(80): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(81): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(82): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(83): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(84): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(89): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(91): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(93): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(95): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(97): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(99): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(101): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(103): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(105): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(107): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(109): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(111): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL Always Construct warning at clock.v(74): variable "dataout_buf[2]" may not be assigned a new value in every possible path through the Always Construct.  Variable "dataout_buf[2]" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at clock.v(74): variable "dataout_buf[5]" may not be assigned a new value in every possible path through the Always Construct.  Variable "dataout_buf[5]" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: "cnt_scan[0]~0"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 26 buffer(s)
    Info: Ignored 26 SOFT buffer(s)
Info: Registers with preset signals will power-up high
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
    Info: Promoted clear signal driven by pin "rst" to global clear signal
Info: Implemented 117 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 16 output pins
    Info: Implemented 95 macrocells
    Info: Implemented 4 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 33 warnings
    Info: Processing ended: Wed Dec 14 14:45:21 2005
    Info: Elapsed time: 00:00:13