iis_vhdl.fit.qmsg

VHDL实现了IIS接口程序

{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "CLKIN Global clock in PIN 10 " "Info: Automatically promoted some destinations of signal \"CLKIN\" to use Global clock in PIN 10" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CS5340_MCLK " "Info: Destination \"CS5340_MCLK\" may be non-global or may not use global clock" {  } { { "IIS_VHDL.vhd" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/IIS_VHDL.vhd" 13 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "IIS_VHDL.vhd" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/IIS_VHDL.vhd" 9 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "altera_internal_jtag~TCKUTAP Global clock " "Info: Automatically promoted signal \"altera_internal_jtag~TCKUTAP\" to use Global clock" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "CS5340_SCLK Global clock " "Info: Automatically promoted some destinations of signal \"CS5340_SCLK\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_signaltap:IIS_VHDL\|acq_trigger_in_reg\[26\] " "Info: Destination \"sld_signaltap:IIS_VHDL\|acq_trigger_in_reg\[26\]\" may be non-global or may not use global clock" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" 573 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "IIS_VHDL.vhd" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/IIS_VHDL.vhd" 11 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "CS5340_SCLK " "Info: Pin \"CS5340_SCLK\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "IIS_VHDL.vhd" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/IIS_VHDL.vhd" 11 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CS5340_SCLK" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CS5340_SCLK } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CS5340_SCLK } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_signaltap:IIS_VHDL\|reset_all Global clock " "Info: Automatically promoted some destinations of signal \"sld_signaltap:IIS_VHDL\|reset_all\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_signaltap:IIS_VHDL\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset " "Info: Destination \"sld_signaltap:IIS_VHDL\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset\" may be non-global or may not use global clock" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_acquisition_buffer.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_acquisition_buffer.vhd" 417 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" 426 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|CLR_SIGNAL Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|CLR_SIGNAL\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_signaltap:IIS_VHDL\|reset_all " "Info: Destination \"sld_signaltap:IIS_VHDL\|reset_all\" may be non-global or may not use global clock" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" 426 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_signaltap:IIS_VHDL\|sld_ela_control:ela_control\|gen_non_zero_sample_depth~0 " "Info: Destination \"sld_signaltap:IIS_VHDL\|sld_ela_control:ela_control\|gen_non_zero_sample_depth~0\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" may be non-global or may not use global clock" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\]\" may be non-global or may not use global clock" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sld_signaltap:IIS_VHDL\|sld_ela_control:ela_control\|gen_non_zero_sample_depth~0 Global clock " "Info: Automatically promoted signal \"sld_signaltap:IIS_VHDL\|sld_ela_control:ela_control\|gen_non_zero_sample_depth~0\" to use Global clock" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_signaltap:IIS_VHDL\|sld_ela_control:ela_control\|gen_non_zero_sample_depth~0" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_signaltap:IIS_VHDL|sld_ela_control:ela_control|gen_non_zero_sample_depth~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_signaltap:IIS_VHDL|sld_ela_control:ela_control|gen_non_zero_sample_depth~0 } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sld_signaltap:IIS_VHDL\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset Global clock " "Info: Automatically promoted signal \"sld_signaltap:IIS_VHDL\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset\" to use Global clock" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_acquisition_buffer.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_acquisition_buffer.vhd" 417 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}