iis_vhdl.map.rpt

VHDL实现了IIS接口程序

Analysis & Synthesis report for IIS_VHDL
Fri Mar 30 16:09:52 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. General Register Statistics
  9. Inverted Register Statistics
 10. Multiplexer Restructuring Statistics (Restructuring Performed)
 11. Source assignments for Top-level Entity: |IIS_VHDL
 12. Source assignments for sld_signaltap:IIS_VHDL
 13. Source assignments for sld_signaltap:IIS_VHDL|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9mi2:auto_generated
 14. Source assignments for sld_signaltap:IIS_VHDL|sld_rom_sr:crc_rom_sr
 15. Source assignments for sld_hub:sld_hub_inst
 16. Source assignments for sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine
 17. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 18. Parameter Settings for Inferred Entity Instance: sld_signaltap:IIS_VHDL
 19. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 20. SignalTap II Logic Analyzer Settings
 21. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Mar 30 16:09:52 2007    ;
; Quartus II Version          ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name               ; IIS_VHDL                                 ;
; Top-level Entity Name       ; IIS_VHDL                                 ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 616                                      ;
; Total pins                  ; 38                                       ;
; Total virtual pins          ; 0                                        ;