iis_vhdl.vhd

VHDL实现了IIS接口程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;


ENTITY IIS_VHDL IS
	PORT(
			CLKIN: IN STD_LOGIC;
			CS5340_DOUT: IN STD_LOGIC;
			CS5340_SCLK: IN STD_LOGIC;
			CS5340_LRCK: IN STD_LOGIC;
			CS5340_MCLK: OUT STD_LOGIC;	
			DNUM:  	 OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
			DATAOUT: OUT STD_LOGIC_VECTOR(23 DOWNTO 0)		
		);
END IIS_VHDL;

ARCHITECTURE RTL OF IIS_VHDL IS
SIGNAL LRCK:STD_LOGIC;
SIGNAL CS5340_Data:STD_LOGIC_VECTOR(23 DOWNTO 0);

BEGIN 
DATAOUT<=CS5340_Data;
CS5340_MCLK<=CLKIN;


RIGHT_LRCK:
	PROCESS(CS5340_LRCK,CS5340_SCLK)
	 VARIABLE DataNum: INTEGER RANGE 0 TO 24:=0;
	 BEGIN
		IF(CS5340_SCLK'EVENT AND CS5340_SCLK='1') THEN
			IF(CS5340_LRCK/=LRCK) THEN
				 DataNum:=0;
			ELSE 
				IF (DataNum<=23) THEN
					CS5340_Data(23-DataNum)<=CS5340_DOUT;
					DataNum:=DataNum+1;
				ELSE 
					DataNum:=DataNum+1;		
				END IF;	
			END IF;	
			LRCK<=CS5340_LRCK;
			DNUM<=CONV_STD_LOGIC_VECTOR(DataNum,5);
		END IF;
	END PROCESS;
END RTL;