mux2_1b.v

来自「《Verilog HDL 程序设计教程》4」· Verilog 代码 · 共 11 行

module mux2_1b(out,a,b,sel);
output out;
input a,b,sel;
reg out;
always @(a or b or sel)
begin
    if(sel) out = b;
    else    out = a;
end
endmodule