add4_3.v

来自「《Verilog HDL 程序设计教程》4」· Verilog 代码 · 共 14 行

module add4_3(cout,sum,a,b,cin);
output[3:0] sum;
output cout;
input[3:0] a,b;
input cin;
reg[3:0] sum;
reg cout;

always @(a or b or cin)
begin
{cout,sum}=a+b+cin;
end
endmodule