paral1.v

来自「《Verilog HDL 程序设计教程》3」· Verilog 代码 · 共 16 行

module paral1(q,a,clk);
output q,a;
input clk;
reg q,a;

always @(posedge clk)
begin
q=~q;
end

always @(posedge clk)
begin
a=~q;
end
endmodule