wave1.v

来自「《Verilog HDL 程序设计教程》2」· Verilog 代码 · 共 17 行

`timescale 10ns/1ns
module wave1;
reg wave;
parameter cycle=10;
initial
  begin
            wave=0;
#(cycle/2)  wave=1;
#(cycle/2)  wave=0;
#(cycle/2)  wave=1;
#(cycle/2)  wave=0;
#(cycle/2)  wave=1;
#(cycle/2)  $finish ;
end
initial $monitor($time,,,"wave=%b",wave);
endmodule