block.v

来自「《Verilog HDL 程序设计教程》2」· Verilog 代码 · 共 11 行

module block(c,b,a,clk);
output c,b;
input clk,a;
reg c,b;
always @(posedge clk)
  begin
  b=a;
  c=b;
  end
endmodule