mux_casez.v

来自「《Verilog HDL 程序设计教程》2」· Verilog 代码 · 共 17 行

module mux_casez(out,a,b,c,d,select);
output out;
input a,b,c,d;
input[3:0] select;
reg out;

always @(select or a or b or c or d)
begin
casez(select)
4'b???1: out = a;
4'b??1?: out = b;
4'b?1??: out = c;
4'b1???: out = d;
endcase
end
endmodule