hh.map.qmsg

用VHDL 语言描述频率计的设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 21 16:05:38 2007 " "Info: Processing started: Thu Jun 21 16:05:38 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off hh -c hh " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off hh -c hh" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hh.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file hh.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 hh-ONE " "Info: Found design unit 1: hh-ONE" {  } { { "hh.vhd" "" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 hh " "Info: Found entity 1: hh" {  } { { "hh.vhd" "" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "hh " "Info: Elaborating entity \"hh\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "OUTX4 hh.vhd(43) " "Warning (10036): Verilog HDL or VHDL warning at hh.vhd(43): object \"OUTX4\" assigned a value but never read" {  } { { "hh.vhd" "" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 43 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "TESTFRE.vhd 2 1 " "Warning: Using design file TESTFRE.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 TESTFRE-ONE " "Info: Found design unit 1: TESTFRE-ONE" {  } { { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/hh/TESTFRE.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 TESTFRE " "Info: Found entity 1: TESTFRE" {  } { { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/hh/TESTFRE.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "TESTFRE TESTFRE:T " "Info: Elaborating entity \"TESTFRE\" for hierarchy \"TESTFRE:T\"" {  } { { "hh.vhd" "T" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 48 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "CNT10.vhd 2 1 " "Warning: Using design file CNT10.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CNT10-ONE " "Info: Found design unit 1: CNT10-ONE" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 CNT10 " "Info: Found entity 1: CNT10" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CNT10 CNT10:C0 " "Info: Elaborating entity \"CNT10\" for hierarchy \"CNT10:C0\"" {  } { { "hh.vhd" "C0" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 54 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "SS CNT10.vhd(24) " "Warning (10492): VHDL Process Statement warning at CNT10.vhd(24): signal \"SS\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "REG4.vhd 2 1 " "Warning: Using design file REG4.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG4-ONE " "Info: Found design unit 1: REG4-ONE" {  } { { "REG4.vhd" "" { Text "F:/临时/EDA/课程设计/hh/REG4.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 REG4 " "Info: Found entity 1: REG4" {  } { { "REG4.vhd" "" { Text "F:/临时/EDA/课程设计/hh/REG4.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG4 REG4:R1 " "Info: Elaborating entity \"REG4\" for hierarchy \"REG4:R1\"" {  } { { "hh.vhd" "R1" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 84 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "SM.vhd 2 1 " "Warning: Using design file SM.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SM-ONE " "Info: Found design unit 1: SM-ONE" {  } { { "SM.vhd" "" { Text "F:/临时/EDA/课程设计/hh/SM.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 SM " "Info: Found entity 1: SM" {  } { { "SM.vhd" "" { Text "F:/临时/EDA/课程设计/hh/SM.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SM SM:SM1 " "Info: Elaborating entity \"SM\" for hierarchy \"SM:SM1\"" {  } { { "hh.vhd" "SM1" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 101 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "LED0\[0\] GND " "Warning: Pin \"LED0\[0\]\" stuck at GND" {  } { { "hh.vhd" "" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LED1\[0\] GND " "Warning: Pin \"LED1\[0\]\" stuck at GND" {  } { { "hh.vhd" "" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 8 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LED2\[0\] GND " "Warning: Pin \"LED2\[0\]\" stuck at GND" {  } { { "hh.vhd" "" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LED3\[0\] GND " "Warning: Pin \"LED3\[0\]\" stuck at GND" {  } { { "hh.vhd" "" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "99 " "Info: Implemented 99 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "32 " "Info: Implemented 32 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "65 " "Info: Implemented 65 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 21 16:05:42 2007 " "Info: Processing ended: Thu Jun 21 16:05:42 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}