hh.hier_info

用VHDL 语言描述频率计的设计

|hh
CLK1 => TESTFRE:T.CLKK
UCLK => CNT10:C0.CLK
LED0[0] <= SM:SM1.O[0]
LED0[1] <= SM:SM1.O[1]
LED0[2] <= SM:SM1.O[2]
LED0[3] <= SM:SM1.O[3]
LED0[4] <= SM:SM1.O[4]
LED0[5] <= SM:SM1.O[5]
LED0[6] <= SM:SM1.O[6]
LED0[7] <= SM:SM1.O[7]
LED1[0] <= SM:SM2.O[0]
LED1[1] <= SM:SM2.O[1]
LED1[2] <= SM:SM2.O[2]
LED1[3] <= SM:SM2.O[3]
LED1[4] <= SM:SM2.O[4]
LED1[5] <= SM:SM2.O[5]
LED1[6] <= SM:SM2.O[6]
LED1[7] <= SM:SM2.O[7]
LED2[0] <= SM:SM3.O[0]
LED2[1] <= SM:SM3.O[1]
LED2[2] <= SM:SM3.O[2]
LED2[3] <= SM:SM3.O[3]
LED2[4] <= SM:SM3.O[4]
LED2[5] <= SM:SM3.O[5]
LED2[6] <= SM:SM3.O[6]
LED2[7] <= SM:SM3.O[7]
LED3[0] <= SM:SM4.O[0]
LED3[1] <= SM:SM4.O[1]
LED3[2] <= SM:SM4.O[2]
LED3[3] <= SM:SM4.O[3]
LED3[4] <= SM:SM4.O[4]
LED3[5] <= SM:SM4.O[5]
LED3[6] <= SM:SM4.O[6]
LED3[7] <= SM:SM4.O[7]


|hh|TESTFRE:T
CLKK => div2clk.CLK
CLKK => process1~0.IN1
ENC <= div2clk.DB_MAX_OUTPUT_PORT_TYPE
RSTC <= process1~0.DB_MAX_OUTPUT_PORT_TYPE
LOADC <= div2clk.DB_MAX_OUTPUT_PORT_TYPE


|hh|CNT10:C0
CLK => SS[2].CLK
CLK => SS[1].CLK
CLK => SS[0].CLK
CLK => OUTY~reg0.CLK
CLK => SS[3].CLK
RST => SS[2].ACLR
RST => SS[1].ACLR
RST => SS[0].ACLR
RST => OUTY~reg0.ACLR
RST => SS[3].ACLR
EN => SS[2].ENA
EN => SS[1].ENA
EN => SS[0].ENA
EN => OUTY~reg0.ENA
EN => SS[3].ENA
OUTX[0] <= SS[0].DB_MAX_OUTPUT_PORT_TYPE
OUTX[1] <= SS[1].DB_MAX_OUTPUT_PORT_TYPE
OUTX[2] <= SS[2].DB_MAX_OUTPUT_PORT_TYPE
OUTX[3] <= SS[3].DB_MAX_OUTPUT_PORT_TYPE
OUTY <= OUTY~reg0.DB_MAX_OUTPUT_PORT_TYPE


|hh|CNT10:C1
CLK => SS[2].CLK
CLK => SS[1].CLK
CLK => SS[0].CLK
CLK => OUTY~reg0.CLK
CLK => SS[3].CLK
RST => SS[2].ACLR
RST => SS[1].ACLR
RST => SS[0].ACLR
RST => OUTY~reg0.ACLR
RST => SS[3].ACLR
EN => SS[2].ENA
EN => SS[1].ENA
EN => SS[0].ENA
EN => OUTY~reg0.ENA
EN => SS[3].ENA
OUTX[0] <= SS[0].DB_MAX_OUTPUT_PORT_TYPE
OUTX[1] <= SS[1].DB_MAX_OUTPUT_PORT_TYPE
OUTX[2] <= SS[2].DB_MAX_OUTPUT_PORT_TYPE
OUTX[3] <= SS[3].DB_MAX_OUTPUT_PORT_TYPE
OUTY <= OUTY~reg0.DB_MAX_OUTPUT_PORT_TYPE


|hh|CNT10:C2
CLK => SS[2].CLK
CLK => SS[1].CLK
CLK => SS[0].CLK
CLK => OUTY~reg0.CLK
CLK => SS[3].CLK
RST => SS[2].ACLR
RST => SS[1].ACLR
RST => SS[0].ACLR
RST => OUTY~reg0.ACLR
RST => SS[3].ACLR
EN => SS[2].ENA
EN => SS[1].ENA
EN => SS[0].ENA
EN => OUTY~reg0.ENA
EN => SS[3].ENA
OUTX[0] <= SS[0].DB_MAX_OUTPUT_PORT_TYPE
OUTX[1] <= SS[1].DB_MAX_OUTPUT_PORT_TYPE
OUTX[2] <= SS[2].DB_MAX_OUTPUT_PORT_TYPE
OUTX[3] <= SS[3].DB_MAX_OUTPUT_PORT_TYPE
OUTY <= OUTY~reg0.DB_MAX_OUTPUT_PORT_TYPE


|hh|CNT10:C3
CLK => SS[2].CLK
CLK => SS[1].CLK
CLK => SS[0].CLK
CLK => OUTY~reg0.CLK
CLK => SS[3].CLK
RST => SS[2].ACLR
RST => SS[1].ACLR
RST => SS[0].ACLR
RST => OUTY~reg0.ACLR
RST => SS[3].ACLR
EN => SS[2].ENA
EN => SS[1].ENA
EN => SS[0].ENA
EN => OUTY~reg0.ENA
EN => SS[3].ENA
OUTX[0] <= SS[0].DB_MAX_OUTPUT_PORT_TYPE
OUTX[1] <= SS[1].DB_MAX_OUTPUT_PORT_TYPE
OUTX[2] <= SS[2].DB_MAX_OUTPUT_PORT_TYPE
OUTX[3] <= SS[3].DB_MAX_OUTPUT_PORT_TYPE
OUTY <= OUTY~reg0.DB_MAX_OUTPUT_PORT_TYPE


|hh|CNT10:C4
CLK => SS[2].CLK
CLK => SS[1].CLK
CLK => SS[0].CLK
CLK => OUTY~reg0.CLK
CLK => SS[3].CLK
RST => SS[2].ACLR
RST => SS[1].ACLR
RST => SS[0].ACLR
RST => OUTY~reg0.ACLR
RST => SS[3].ACLR
EN => SS[2].ENA
EN => SS[1].ENA
EN => SS[0].ENA
EN => OUTY~reg0.ENA
EN => SS[3].ENA
OUTX[0] <= SS[0].DB_MAX_OUTPUT_PORT_TYPE
OUTX[1] <= SS[1].DB_MAX_OUTPUT_PORT_TYPE
OUTX[2] <= SS[2].DB_MAX_OUTPUT_PORT_TYPE
OUTX[3] <= SS[3].DB_MAX_OUTPUT_PORT_TYPE
OUTY <= OUTY~reg0.DB_MAX_OUTPUT_PORT_TYPE


|hh|REG4:R1
LOAD => DOUT[2]~reg0.CLK
LOAD => DOUT[1]~reg0.CLK
LOAD => DOUT[0]~reg0.CLK
LOAD => DOUT[3]~reg0.CLK
DIN[0] => DOUT[0]~reg0.DATAIN
DIN[1] => DOUT[1]~reg0.DATAIN
DIN[2] => DOUT[2]~reg0.DATAIN
DIN[3] => DOUT[3]~reg0.DATAIN
DOUT[0] <= DOUT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[1] <= DOUT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[2] <= DOUT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[3] <= DOUT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|hh|REG4:R2
LOAD => DOUT[2]~reg0.CLK
LOAD => DOUT[1]~reg0.CLK
LOAD => DOUT[0]~reg0.CLK
LOAD => DOUT[3]~reg0.CLK
DIN[0] => DOUT[0]~reg0.DATAIN
DIN[1] => DOUT[1]~reg0.DATAIN
DIN[2] => DOUT[2]~reg0.DATAIN
DIN[3] => DOUT[3]~reg0.DATAIN
DOUT[0] <= DOUT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[1] <= DOUT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[2] <= DOUT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[3] <= DOUT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|hh|REG4:R3
LOAD => DOUT[2]~reg0.CLK
LOAD => DOUT[1]~reg0.CLK
LOAD => DOUT[0]~reg0.CLK
LOAD => DOUT[3]~reg0.CLK
DIN[0] => DOUT[0]~reg0.DATAIN
DIN[1] => DOUT[1]~reg0.DATAIN
DIN[2] => DOUT[2]~reg0.DATAIN
DIN[3] => DOUT[3]~reg0.DATAIN
DOUT[0] <= DOUT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[1] <= DOUT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[2] <= DOUT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[3] <= DOUT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|hh|REG4:R4
LOAD => DOUT[2]~reg0.CLK
LOAD => DOUT[1]~reg0.CLK
LOAD => DOUT[0]~reg0.CLK
LOAD => DOUT[3]~reg0.CLK
DIN[0] => DOUT[0]~reg0.DATAIN
DIN[1] => DOUT[1]~reg0.DATAIN
DIN[2] => DOUT[2]~reg0.DATAIN
DIN[3] => DOUT[3]~reg0.DATAIN
DOUT[0] <= DOUT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[1] <= DOUT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[2] <= DOUT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[3] <= DOUT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|hh|SM:SM1
I[0] => Mux~0.IN19
I[0] => Mux~1.IN19
I[0] => Mux~2.IN19
I[0] => Mux~3.IN19
I[0] => Mux~4.IN19
I[0] => Mux~5.IN19
I[0] => Mux~6.IN19
I[1] => Mux~0.IN18
I[1] => Mux~1.IN18
I[1] => Mux~2.IN18
I[1] => Mux~3.IN18
I[1] => Mux~4.IN18
I[1] => Mux~5.IN18
I[1] => Mux~6.IN18
I[2] => Mux~0.IN17
I[2] => Mux~1.IN17
I[2] => Mux~2.IN17
I[2] => Mux~3.IN17
I[2] => Mux~4.IN17
I[2] => Mux~5.IN17
I[2] => Mux~6.IN17
I[3] => Mux~0.IN16
I[3] => Mux~1.IN16
I[3] => Mux~2.IN16
I[3] => Mux~3.IN16
I[3] => Mux~4.IN16
I[3] => Mux~5.IN16
I[3] => Mux~6.IN16
O[0] <= <GND>
O[1] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
O[2] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
O[3] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
O[4] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
O[5] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
O[6] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
O[7] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE


|hh|SM:SM2
I[0] => Mux~0.IN19
I[0] => Mux~1.IN19
I[0] => Mux~2.IN19
I[0] => Mux~3.IN19
I[0] => Mux~4.IN19
I[0] => Mux~5.IN19
I[0] => Mux~6.IN19
I[1] => Mux~0.IN18
I[1] => Mux~1.IN18
I[1] => Mux~2.IN18
I[1] => Mux~3.IN18
I[1] => Mux~4.IN18
I[1] => Mux~5.IN18
I[1] => Mux~6.IN18
I[2] => Mux~0.IN17
I[2] => Mux~1.IN17
I[2] => Mux~2.IN17
I[2] => Mux~3.IN17
I[2] => Mux~4.IN17
I[2] => Mux~5.IN17
I[2] => Mux~6.IN17
I[3] => Mux~0.IN16
I[3] => Mux~1.IN16
I[3] => Mux~2.IN16
I[3] => Mux~3.IN16
I[3] => Mux~4.IN16
I[3] => Mux~5.IN16
I[3] => Mux~6.IN16
O[0] <= <GND>
O[1] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
O[2] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
O[3] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
O[4] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
O[5] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
O[6] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
O[7] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE


|hh|SM:SM3
I[0] => Mux~0.IN19
I[0] => Mux~1.IN19
I[0] => Mux~2.IN19
I[0] => Mux~3.IN19
I[0] => Mux~4.IN19
I[0] => Mux~5.IN19
I[0] => Mux~6.IN19
I[1] => Mux~0.IN18
I[1] => Mux~1.IN18
I[1] => Mux~2.IN18
I[1] => Mux~3.IN18
I[1] => Mux~4.IN18
I[1] => Mux~5.IN18
I[1] => Mux~6.IN18
I[2] => Mux~0.IN17
I[2] => Mux~1.IN17
I[2] => Mux~2.IN17
I[2] => Mux~3.IN17
I[2] => Mux~4.IN17
I[2] => Mux~5.IN17
I[2] => Mux~6.IN17
I[3] => Mux~0.IN16
I[3] => Mux~1.IN16
I[3] => Mux~2.IN16
I[3] => Mux~3.IN16
I[3] => Mux~4.IN16
I[3] => Mux~5.IN16
I[3] => Mux~6.IN16
O[0] <= <GND>
O[1] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
O[2] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
O[3] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
O[4] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
O[5] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
O[6] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
O[7] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE


|hh|SM:SM4
I[0] => Mux~0.IN19
I[0] => Mux~1.IN19
I[0] => Mux~2.IN19
I[0] => Mux~3.IN19
I[0] => Mux~4.IN19
I[0] => Mux~5.IN19
I[0] => Mux~6.IN19
I[1] => Mux~0.IN18
I[1] => Mux~1.IN18
I[1] => Mux~2.IN18
I[1] => Mux~3.IN18
I[1] => Mux~4.IN18
I[1] => Mux~5.IN18
I[1] => Mux~6.IN18
I[2] => Mux~0.IN17
I[2] => Mux~1.IN17
I[2] => Mux~2.IN17
I[2] => Mux~3.IN17
I[2] => Mux~4.IN17
I[2] => Mux~5.IN17
I[2] => Mux~6.IN17
I[3] => Mux~0.IN16
I[3] => Mux~1.IN16
I[3] => Mux~2.IN16
I[3] => Mux~3.IN16
I[3] => Mux~4.IN16
I[3] => Mux~5.IN16
I[3] => Mux~6.IN16
O[0] <= <GND>
O[1] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
O[2] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
O[3] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
O[4] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
O[5] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
O[6] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
O[7] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE