hh.fit.qmsg

用VHDL 语言描述频率计的设计

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "UCLK Global clock in PIN 17 " "Info: Automatically promoted signal \"UCLK\" to use Global clock in PIN 17" {  } { { "hh.vhd" "" { Text "F:/临时/EDA/课程设计/hh/hh.vhd" 6 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "TESTFRE:T\|div2clk Global clock " "Info: Automatically promoted some destinations of signal \"TESTFRE:T\|div2clk\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CNT10:C0\|SS\[0\] " "Info: Destination \"CNT10:C0\|SS\[0\]\" may be non-global or may not use global clock" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 16 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "TESTFRE:T\|div2clk " "Info: Destination \"TESTFRE:T\|div2clk\" may be non-global or may not use global clock" {  } { { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/hh/TESTFRE.vhd" 14 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CNT10:C0\|SS\[1\] " "Info: Destination \"CNT10:C0\|SS\[1\]\" may be non-global or may not use global clock" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 16 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CNT10:C0\|SS\[2\] " "Info: Destination \"CNT10:C0\|SS\[2\]\" may be non-global or may not use global clock" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 16 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CNT10:C0\|SS\[3\] " "Info: Destination \"CNT10:C0\|SS\[3\]\" may be non-global or may not use global clock" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 16 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CNT10:C1\|SS\[0\] " "Info: Destination \"CNT10:C1\|SS\[0\]\" may be non-global or may not use global clock" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 16 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CNT10:C1\|SS\[1\] " "Info: Destination \"CNT10:C1\|SS\[1\]\" may be non-global or may not use global clock" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 16 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CNT10:C1\|SS\[2\] " "Info: Destination \"CNT10:C1\|SS\[2\]\" may be non-global or may not use global clock" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 16 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CNT10:C1\|SS\[3\] " "Info: Destination \"CNT10:C1\|SS\[3\]\" may be non-global or may not use global clock" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 16 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CNT10:C2\|SS\[0\] " "Info: Destination \"CNT10:C2\|SS\[0\]\" may be non-global or may not use global clock" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 16 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0}  } { { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/hh/TESTFRE.vhd" 14 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CNT10:C0\|OUTY Global clock " "Info: Automatically promoted signal \"CNT10:C0\|OUTY\" to use Global clock" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 9 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CNT10:C1\|OUTY Global clock " "Info: Automatically promoted signal \"CNT10:C1\|OUTY\" to use Global clock" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 9 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CNT10:C2\|OUTY Global clock " "Info: Automatically promoted signal \"CNT10:C2\|OUTY\" to use Global clock" {  } { { "CNT10.vhd" "" { Text "F:/临时/EDA/课程设计/hh/CNT10.vhd" 9 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "TESTFRE:T\|RSTC Global clock " "Info: Automatically promoted signal \"TESTFRE:T\|RSTC\" to use Global clock" {  } { { "TESTFRE.vhd" "" { Text "F:/临时/EDA/课程设计/hh/TESTFRE.vhd" 6 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0 0 "Started Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0 0 "Finished Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 0 0}